AD14160/AD14160L

–33–

REV. A

Serial Ports

40 MHz–5 V

40 MHz–3.3 V

Parameter

Min

Max

Min

Max

Units

External Clock

Timing Requirements:

TFS/RFS Setup Before TCLK/RCLK

1

3.5

3.5

ns

TFS/RFS Hold After TCLK/RCLK

1, 2

44

ns

Receive Data Setup Before RCLK

1

1.5

1.5

ns

Receive Data Hold After RCLK

1

44

ns

TCLK/RCLK Width

9.5

9

ns

TCLK/RCLK Period

ns

Internal Clock

Timing Requirements:

TFS Setup Before TCLK

ns

TFS/RFS Hold After TCLK/RCLK

1, 2

11

ns

Receive Data Setup Before RCLK

1

33

ns

Receive Data Hold After RCLK

1

33

ns

External or Internal Clock

Switching Characteristics:

RFS Delay After RCLK (Internally Generated RFS)

3

13.5

13.5

ns

RFS Hold After RCLK (Internally Generated RFS)

3

33

ns

External Clock

Switching Characteristics:

TFS Delay After TCLK (Internally Generated TFS)

3

13.5

13.5

ns

TFS Hold After TCLK (Internally Generated TFS)

3

33

ns

Transmit Data Delay After TCLK

3

16.5

16.5

ns

Transmit Data Hold After TCLK

3

55

ns

Internal Clock

Switching Characteristics:

TFS Delay After TCLK (Internally Generated TFS)

3

4.5

4.5

ns

TFS Hold After TCLK (Internally Generated TFS)

3

–1.5

–1.5

ns

Transmit Data Delay After TCLK

3

7.5

7.5

ns

Transmit Data Hold After TCLK

3

00

ns

TCLK/RCLK Width

(SCLK/2) – 2

(SCLK/2) + 2

(SCLK/2) – 2.5

(SCLK/2) + 2.5

ns

Enable and Three-State

Switching Characteristics:

Data Enable from External TCLK

3

3.5

4

ns

Data Disable from External TCLK

3

11

11

ns

Data Enable from Internal TCLK

3

00

ns

Data Disable from Internal TCLK

3

33

ns

TCLK/RCLK Delay from CLKIN

22.5 + 3DT/8

22.5 + 3DT/8

ns

SPORT Disable After CLKIN

17.5

17.5

ns

External Late Frame Sync

Switching Characteristics:

12.5

13.3

ns

External RFS with MCE = 1, MFD = 0

4

4

3

3.5

ns

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame

sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.

NOTES