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AD1819B Datasheet(PDF) 6 Page - Analog Devices |
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AD1819B Datasheet(HTML) 6 Page - Analog Devices |
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6 / 28 page  AD1819B –6– REV. 0 TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE) Parameter Symbol Min Typ Max Units RESET Active Low Pulsewidth tRST_LOW 1.0 µs RESET Inactive to BIT_CLK Start-Up Delay tRST2CLK 162.8 ns SYNC Active High Pulsewidth tSYNC_HIGH 0.0814 1.3 µs SYNC Low Pulsewidth tSYNC_LOW 19.5 µs SYNC Inactive to BIT_CLK Start-Up Delay tSYNC2CLK 162.8 ns BIT_CLK Frequency 12.288 MHz BIT_CLK Period tCLK_PERIOD 81.4 ns BIT_CLK Output Jitter* 750 ps BIT_CLK High Pulsewidth tCLK_HIGH 32.56 40.7 48.84 ns BIT_CLK Low Pulsewidth tCLK_LOW 32.56 40.7 48.84 ns SYNC Frequency 48.0 kHz SYNC Period tSYNC_PERIOD 20.8 µs Setup to Falling Edge of BIT_CLK tSETUP 15.0 ns Hold from Falling Edge of BIT_CLK tHOLD 15.0 ns BIT_CLK Rise Time tRISE CLK 4ns BIT_CLK Fall Time tFALL CLK 4ns SYNC Rise Time tRISE SYNC 4ns SYNC Fall Time tFALL SYNC 4ns SDATA_IN Rise Time tRISE DIN 4ns SDATA_IN Fall Time tFALL DIN 4ns SDATA_OUT Rise Time tRISE DOUT 4ns SDATA_OUT Fall Time tFALL DOUT 4ns End of Slot 2 to BIT_CLK, SDATA_IN Low tS2_PDOWN 1.0 µs Setup to Trailing Edge of RESET (Applies to SYNC, SDATA_OUT) tSETUP2RST 15 ns Rising Edge of RESET to HI-Z Delay tOFF 25 ns *Output Jitter is directly dependent on crystal input jitter. RESET BIT_CLK tRST2CLK tRST_LOW Figure 1. Cold Reset SYNC BIT_CLK tSYNC_HIGH tRST2CLK Figure 2. Warm Reset tCLK_HIGH BIT_CLK tCLK_LOW SYNC tSYNC_HIGH tSYNC_LOW tSYNC_PERIOD tCLK_PERIOD Figure 3. Clock Timing |
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