AD1819B

–17–

REV. 0

Serial Configuration (Index 74h)

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

4

7n

o

i

t

a

r

u

g

i

f

n

o

C

l

a

i

r

e

S

T

O

L

S

6

1

M

G

E

R

2

M

G

E

R

1

M

G

E

R

0

E

Q

R

D

N

Q

R

L

D

2

Q

R

L

D

1

Q

R

L

D

0

XXXXX

Q

R

R

D

2

Q

R

R

D

1

Q

R

R

D

0

h

0

0

0

7

DRRQ0

Master AC’97 Codec DAC Right Request.

DRRQ1

Slave 1 Codec DAC Right Request.

DRRQ2

Slave 2 Codec DAC Right Request.

DLRQ0

Master AC’97 Codec DAC Left Request.

DLRQ1

Slave 1 Codec DAC Left Request.

DLRQ2

Slave 2 Codec DAC Left Request.

DRQEN

Fills idle status slots with DAC request reads, and stuffs DAC requests into LSB of output address slot. (AC-Link

Slot 1.)

REGM0

Master Codec Register Mask.

REGM1

Slave 1 Codec Register Mask.

REGM2

Slave 2 Codec Register Mask.

SLOT16

Enable 16-Bit Slots.

If your system uses only a single AD1819B, you can ignore the register mask and the slave 1/slave 2 request bits. If

you write to this register, write ones to all of the register mask bits. The request bits are read-only.

The codec asserts each request bit when the corresponding DAC channel can accept data in the next frame. These

bits are snapshots of the codec state taken when the current frame began (effectively, on the rising edge of SYNC),

but they also take notice of DAC samples sent in the current frame.

If you set the DRQEN bit, the AD1819B will fill all otherwise unused AC-Link status address and data slots with

the contents of register 74h. That makes it somewhat simpler to access the information, because you don’t need to

continually issue AC-Link read commands to get the register contents.

Also, the DAC requests are reflected in Slot 1, Bits (11 . . . 6). These bits are active Lo.

SLOT16 makes all AC-Link slots 16 bits in length, formatted into 16 slots.

Miscellaneous Control Bits (Index 76h)

g

e

R

m

u

N

e

m

a

N5

1

D4

1

D3

1

D2

1

D1

1

D0

1

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Dt

l

u

a

f

e

D

h

6

7s

t

i

B

l

o

r

t

n

o

C

c

s

i

MZ

C

A

D

XXXX

R

S

L

DX

R

S

L

A

D

O

M

N

E

0

1

X

R

S

7

D

8

X

R

S

7

D

XX

R

S

R

DX

R

S

R

Ah

0

0

0

0

ARSR

ADC Right Sample Generator Select. Connects right ADC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.

DRSR

DAC Right Sample Generator Select. Connects right DAC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.

SRX8D7

Multiply SR1 Rate by 8/7.

SRX10D7

Multiply SR1 Rate by 10/7. SRX10D7 and SRX8D7 are mutually exclusive; SRX10D7 has priority if both are set.

MODEN

Modem Filter Enable (left channel only). Change only when DACs are powered down.

ALSR

ADC Left Sample Generator Select. Connects left ADC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.

DLSR

DAC Left Sample Generator Select. Connects left DAC channel to SR0 or SR1.

0 = SR0 Selected.

1 = SR1 Selected.

DACZ

Zero-Fill (vs. repeat sample) if DAC is starved.