AD1870 datasheet(13/20 Pages) AD

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AD1870

REV. 0

–13–

Timing Parameters

For master modes, a BCLK transmitting edge (labeled “XMIT”)

will be delayed from a CLKIN rising edge by tDLYCKB, as shown

in Figure 17. A L

RCK transition will be delayed from a BCLK

transmitting edge by tDLYBLR. A WCLK rising edge will be

delayed from a BCLK transmitting edge by tDLYBWR, and a WCLK

falling edge will be delayed from a BCLK transmitting edge by

tDLYBWF. The DATA and TAG outputs will be delayed from a

transmitting edge of BCLK by tDLYDT.

For slave modes, an L

RCK transition must be setup to a BCLK

sampling edge (labeled “SAMPLE”) by tSETLRBS. The DATA

and TAG outputs will be delayed from an L

RCK transition by

tDLYLRDT, and DATA and TAG outputs will be delayed from

BCLK transmitting edge by tDLYBDT. For “Slave Mode, Data

Position Controlled by WCLK Input,” WCLK must be set up

to a BCLK sampling edge by tSETWBS.

For both master and slave modes, BCLK must have a minimum

LO pulsewidth of tBPWL, and a minimum HI pulsewidth of tBPWH.

The AD1870 CLKIN and

RESET timing is shown in Figure

19. CLKIN must have a minimum LO pulsewidth of tCPWL, and

a minimum HI pulsewidth of tCPWH. The minimum period of

CLKIN is given by tCLKIN. RESET must have a minimum LO

pulsewidth of tRPWL. Note that there are no setup or hold time

requirements for

RESET.

Master Clock (CLKIN) Considerations

It is recommended that the BCLK and L

RCK are derived from

CLKIN to ensure correct phase relationships. The modulator

of the AD1870 runs at 64

× f

S, therefore best performance is

obtained when the BCLK rate equals 64

× fS or 32 × fS. BCLK

rates such as 48

× fS may result in an increased spectral noise

floor, depending on the phase relationship of BCLK to CLKIN.

Synchronizing Multiple AD1870s

Multiple AD1870s can be synchronized by making all the

AD1870s serial port slaves. This option is illustrated in Figure 6.

See the “Reset, Autocalibration, and Power Down” section for

additional information.

#1 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

RCK

CLOCK

SOURCE

#2 AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

RCK

#N AD1870

SLAVE MODE

CLKIN

DATA

BCLK

WCLK

RCK

RESET

Figure 6. Synchronizing Multiple AD1870s

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