AD1876

REV. A

–6–

CLK will continue pulsing. Since the SAMPLE pin has no con-

trol over the actual calibration process, normal conversion tim-

ing may also be used for calibration. In this case, however, the

SAMPLE is LOW. BUSY going LOW will always indicate the

end of calibration.

A calibration sequence should be followed by one “dummy”

conversion to clear the internal circuitry of the AD1876 in order

to guarantee subsequent conversion accuracy.

In most applications, it is sufficient to calibrate the AD1876

only upon power-up, in which case care should be taken that the

power supplies and voltage reference have stabilized first.

CONVERSION CONTROL

The AD1876 is controlled by two signals: SAMPLE and CLK,

as shown in Figure 2. It is assumed that the part has been cali-

brated and the digital I/O pins have the levels shown at the start

of the timing diagram.

A conversion consists of an input acquisition followed by 17

clock pulses which are required to run the 16-bit internal suc-

cessive approximation routine. The analog input is acquired by

taking the SAMPLE line HIGH for a minimum acquisition time

the instant the SAMPLE pin is brought LOW. Care should be

taken to ensure that this negative edge is well defined and jitter

free to reduce the uncertainty (noise) in ac signal acquisition.

On that edge the AD1876 commits itself to the initiated conver-

tor array and the SAMPLE input will be ignored until the

conversion is completed (i.e., BUSY goes LOW). After a delay

applied. BUSY is asserted after the first positive edge on CLK

puts are generated in response to the rising edges of valid CLK

pulses. As indicated in the timing diagram, the 2s complement

output data is presented MSB first. This data may be captured

≥ t

sample is acquired. SAMPLE will no longer be ignored after

BUSY goes LOW, and so an acquisition may be initiated even

during the HIGH time of the 17th CLK pulse for maximum

throughput rate while enabling full settling of the sample/hold

circuitry. Note that if SAMPLE is already HIGH when BUSY

starts from that time.

During signal acquisition and conversion, care should be taken

with the logic inputs to avoid digital feedthrough noise. It is not

continuous CLK is used, then the user must avoid CLK edges

transition disturbing the internal comparator’s settling (whose

decision is latched on the positive edge of each valid CLK). For

the same reason, it is also not recommended that the SAMPLE

pin change state during conversion (i.e., until after BUSY re-

turns LOW).

FUNCTIONAL DESCRIPTION

The AD1876 is a 16-bit analog-to-digital converter including a

sample/hold input circuit, successive approximation register,

ground sensing circuitry, serial output port and a micro-

controller based autocalibration circuit. These functions are seg-

mented onto two monolithic chips, an analog signal processor

and a digital controller. Both chips are contained within the

AD1876 package.

The AD1876 employs a successive-approximation technique to

determine the value of the analog input voltage. However, in-

stead of the traditional laser-trimmed resistor-ladder approach,

the AD1876 uses a capacitor-array, charge-redistribution tech-

nique. An array of binary-weighted capacitors subdivides the

input value to perform the actual analog to digital conversion.

This capacitor array also serves a sample/hold function without

the need for additional external circuitry.

The autocalibration circuit within the AD1876 employs a

microcontroller and calibration DAC to measure and compen-

sate capacitor mismatch errors. As each error is determined, its

value is stored in on-chip memory (RAM). Subsequent conver-

sions use these RAM values to improve conversion accuracy.

The autocalibration routine may be invoked at any time. Auto-

calibration insures high performance while eliminating the need

for any user adjustments, and is described in detail below.

The microcontroller controls all of the various functions within

the AD1876. These include the actual successive approximation

routine, the autocalibration routine, the sample/hold operation,

and the serial data transmission.

AUTOCALIBRATION

The AD1876 achieves rated performance without the need for

user trims or adjustments. This is accomplished through the use

of on-chip autocalibration.

In the autocalibration sequence, sample/hold offset is nulled by

internally connecting the input circuit to the ground sense cir-

cuit. The resulting offset voltage is measured and stored in

RAM for later use. Next, the capacitor representing the most

significant bit (MSB) is charged to the reference voltage. This

charge is then inverted and shared between the MSB capacitor

and one of equal size composed of all the least significant bits.

The difference in the summation of the charges in each of the

equally sized capacitors represents the amount of capacitor mis-

match. A calibration D/A converter (DAC) adds an appropriate

value of error correction voltage to cancel the mismatch. This

correction factor is also stored in RAM. This process is repeated

for each of the capacitors representing the remaining bits. The

accumulated values in RAM are then used during subsequent

conversions to adjust conversion results.

As shown in Figure 1, when CAL is taken HIGH the AD1876

internal circuitry is reset, the BUSY pin is driven HIGH and the

part prepares for calibration. This is a ‘hard’ reset and will inter-

rupt any conversion or calibration currently in progress. In order

to guarantee that all internal undefined states are cleared, the

CAL pin should he held HIGH for at least 4 CLK cycles. Ac-

tual calibration begins when the CAL pin is taken LOW and

completes in less than 5000 clock cycles or about 2.5 msec with

a continuous 500 nsec clock.

During calibration the SAMPLE pin adopts an alternative func-

tion (not intended to be used by the customer). If SAMPLE is