AD7176-2 datasheet(21/68 Pages) AD

21 / 68 page

Data Sheet

AD7176-2

Rev. 0 | Page 21 of 68

ADC Setups

The AD7176-2 has four independent setups (see Block B in

Figure 28). Each setup consists of the following four registers:

•

Setup configuration register

•

Filter configuration register

•

Offset register

•

Gain register

For example, Setup 0 consists of Setup Configuration 0, Filter

Configuration 0, Offset 0, and Gain 0. The setup is selectable

from the channel map registers detailed in the Channel Map

Configuration section. This allows each channel to be assigned

to a separate setup; therefore, each channel is fully configurable

because each setup has its own filter, offset, and gain register.

Table 11 through Table 14 show the four registers that are

associated with Setup 0.

Setup Configuration Register

The setup configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar and unipolar. In

bipolar mode, the ADC accepts negative differential input voltages,

and the output coding is offset binary. In unipolar mode, the ADC

accepts only positive differential voltages, and the coding is straight

binary. In either case, the input voltage must be within the supply

voltages. The user can also select the reference source using this

reference, an external reference connected between REF+ and

REF− pins, or AVDD1 – AVSS.

Filter Configuration Register

The filter configuration register is used to select which digital

filter is used at the output of the ADC modulator. The order of

the filter and the output data rate is selected by setting the bits

in this register. For more information, see the Digital Filters section.

Offset Register

The offset register holds the offset calibration coefficient for the

ADC. The power-on reset value of the offset register is 0x800000.

The offset register is a 24-bit read/write register. The power-on

reset value is automatically overwritten if an internal or system

zero-scale calibration is initiated by the user or if the offset register

is written to by the user.

Gain Register

The gain register is a 24-bit register that holds the gain

calibration coefficient for the ADC. The gain registers are

read/write registers. These registers are configured at power-on

with factory calibrated coefficients. Therefore, every device has

different default coefficients. The default value is automatically

overwritten if a system full-scale calibration is initiated by the

user or if the gain register is written to by the user. For more

information on calibration, see the Operating Modes section.

Table 11. Setup Configuration 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x20 SETUPCON0 [15:8]

RESERVED

BI_UNIPOLAR0

RESERVED

0x1020 RW

[7:0]

RESERVED

REF_SEL0

RESERVED

Table 12. Filter Configuration 0 Register

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x28 FILTCON0

[15:8] SINC3_MAP0

RESERVED

ENHFILTEN0

ENHFILT0

0x0000 RW

[7:0] RESERVED

ORDER0

ODR0

Table 13. Offset 0 Register

Reg Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x30 OFFSET0

[23:16]

OFFSET0[23:16]

0x800000 RW

[15:8]

OFFSET0[15:8]

[7:0]

OFFSET0[7:0]

Table 14. Gain 0 Register

Reg Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x38 GAIN0

[23:16]

GAIN0[23:16]

0x5XXXX0 RW

[15:8]

GAIN0[15:8]

[7:0]

GAIN0[7:0]

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