AD1955

Rev. PrF

-7-

PRELIMINARY TECHNICAL DATA

Left and Right channel data are valid on rising edge of EF_BCLK. After LSB data is clocked in the AD1955, the falling edge of

EF_WCLK signal loads all of data and starts conversion. The mode can be set to Left or Right-justified. A burst mode BCLK is also

acceptable in Left-justified mode.

BC L K

LR C L K

S D AT A

M SB

MS B

L SB

L SB

LE F T C H A N N E L

R I G H T CH A N NE L

L E F T J U S T IF IE D M O D E - 1 6 T O 2 4 - B IT S P E R C H A N N E L

BC L K

LR C L K

S D AT A

M SB

MS B

LS B

L SB

LE F T C H A N N E L

R I G H T CH A N NE L

I2 S M O D E - 1 6 T O 2 4 - B I T S PE R C H A N N E L

BC L K

LR C L K

S D AT A

M SB

MS B

LS B

LS B

LE F T C H A N N E L

R I G H T CH A N NE L

R IG H T J U ST IF I E D M O D E - S EL EC T N U M BE R O F BIT S PER C H A N N EL

BC L K

LR C L K

S D AT A

M SB

MS B

LS B

L SB

DS P M O D E - 1 6 T O 2 4 - B I T S P E R CHA NNE L

NO T E S : 1 . DS P M O DE DO E S N'T ID E N T I F Y CHA NNE L

3 . BC L K F R EQ U E N C Y I S N O R M A L L Y 6 4 x L R C L K BU T M AY BE O PER A T ED I N BU R S T M O D E

2 . L R CL K NO RM A L L Y O P E R A T E S A T F s E X CE P T F O R DS P M O DE W H ICH IS 2 x F s

1/ F s

Figure 1. Supported Serial Data Formats

Figure 2. Serial Data Port Timing