ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

19

II) The second method to reading data from the internal register is to start immediately after writing to the

internal address pointer and the transmission format register. Set 4h to the transmission format register

when this method is used.

Example 2 of data read (when data is read from internal address Dh to 0h)

III) The third method to reading data from the internal register is to start reading immediately after writing

to the slave address(0110010) and the (R/

W) bit. Since the internal address pointer is set to Fh by

default , this method is only effective when reading is started from the internal address Fh.

Example 3 of data read (when data is read from internal address Fh to 3h).

Data Transmission Under Special Condition

The ACE5372 hold the clock tentatively for duration from start condition to stop condition to avoid invalid

read or write clock on carrying clock. To prevent invalid read or write clock shall be made during one

transmission operation. When 0.5 to 1.0 seconds elapses after start condition any access to the ACE5372

is automatically released to release tentative hold of the clock and access from the CPU is forced to be

terminated (automatic resume function from the interface).

Also a second start condition after the first condition and before the stop condition is regarded as the

“repeated start condition”. Therefore, when 0.5 to 1.0 seconds passed after the first start condition,

access to the ACE5372 is automatically released.

CPU to ACE5372

ACE5372 to CPU

Acknowledge signal

Start signal

Stop signal

Repeat Start signal

CPU to ACE5372

ACE5372 to CPU

Acknowledge signal

Start signal

Stop signal

Repeat Start signal

Inform ACE5372 to stop read