AD5262 datasheet(14/20 Pages) AD

14 / 20 page

REV. 0

–14–

AD5260/AD5262

TEST CIRCUITS (continued)

SDI

CLK

VLOGIC

ILOGIC

DIGITAL INPUT

VOLTAGE

Test Circuit 8. VLOGIC Current vs. Digital Input Voltage

VCM

ICM

GND

VSS

VDD

DUT

Test Circuit 9. Analog Crosstalk

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates output voltages at wiper-

to-B and wiper-to-A to be proportional to the input voltage at

A-to-B. Ignore the effect of the wiper resistance at the moment.

For example, connecting A-terminal to 5 V and B-terminal to

ground produces an output voltage at the wiper-to-B starting at

zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal

to the voltage applied across terminal AB divided by the 256 posi-

tion of the potentiometer divider. Since the AD5260/AD5262

operates from dual supplies, the general equation defining the

output voltage at VW with respect to ground for any given input

voltage applied to terminals AB is:

WAB

() =¥ +

256

(3)

Operation of the digital potentiometer in the divider mode results

in more accurate operation over temperature. Unlike the rheostat

mode, the output voltage is dependent on the ratio of the internal

resistors RWA and RWB and not the absolute values; therefore, the

drift reduces to 5 ppm/

∞C.

APPLICATIONS

Bipolar DC or AC Operation from Dual Supplies

The AD5260/AD5262 can be operated from dual supplies enabling

control of ground referenced AC signals or bipolar operation.

The AC signal, as high as VDD/VSS, can be applied directly across

terminals A–B with output taken from terminal W. See Figure 13

for a typical circuit connection.

VSS

+5.0V

CLK

GND

VDD

SDI

GND

VDD

–5.0V

SCLK

MOSI

5V p-p

2.5V p-p

D = 80H

Figure 13. Bipolar Operation from Dual Supplies

Gain Control Compensation

Digital potentiometers are commonly used in gain control as in

the noninverting gain amplifier shown in Figure 14.

200k

4.7pF

47k

25pF

Figure 14. Typical Noninverting Gain Amplifier

Notice that when the RDAC B terminal parasitic capacitance is

connected to the op amp noninverting node, it introduces a zero

for the 1/

bO term with +20 dB/dec, whereas a typical op amp GBP

has –20 dB/dec characteristics. A large R2 and finite C1 can cause

this Zero’s frequency to fall well below the crossover frequency.

Hence the rate of closure becomes 40 dB/dec and the system has

∞ phase margin at the crossover frequency. The output may ring

or oscillate if the input is a rectangular pulse or step function.

Similarly, it is also likely to ring when switching between two

gain values because this is equivalent to a step change at the input.

Depending on the op amp GBP, reducing the feedback resistor

may extend the Zero’s frequency far enough to overcome the prob-

lem. A better approach, however, is to include a compensation

capacitor C2 to cancel the effect caused by C1. Optimum compen-

sation occurs when R1

C1 = R2

C2. This is not an option

because of the variation of R2. As a result, one may use the relation-

ship above and scale C2 as if R2 is at its maximum value. Doing so

may overcompensate and compromise the performance slightly

when R2 is set at low values. However, it will avoid the ringing or

oscillation at the worst case. For critical applications, C2 should

be found empirically to suit the need. In general, C2 in the range

of a few pF to no more than a few tenths of pF is usually adequate

for the compensation.

Similarly, there are W and A terminal capacitances connected to

the output (not shown). Fortunately their effect at this node is less

significant, and the compensation can be avoided in most cases.

Programmable Voltage Reference

For voltage divider mode operation, Figure 15, it is common

to buffer the output of the digital potentiometer unless the load is

much larger than RWB. Not only does the buffer serve the pur-

pose of impedance conversion, but it also allows a heavier load

to be driven.

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