AD5313 datasheet(16/18 Pages) AD

16 / 18 page

REV. 0

AD5303/AD5313/AD5323

–16–

AD5303/AD5313/AD5323 as a Digitally Programmable

Window Detector

A digitally programmable upper/lower limit detector using the

two DACs in the AD5303/AD5313/AD5323 is shown in Figure

42. The upper and lower limits for the test are loaded to DACs

A and B which, in turn, set the limits on the CMP04. If the

signal at the VIN input is not within the programmed window, a

LED will indicate the fail condition.

VREFA

VREFB

SCLK

DIN

SYNC

VDD

GND

VOUTA

VOUTB

+5V

0.1 F

10 F

SCLK

DIN

SYNC

VREF

VIN

1/2

CMP04

FAIL

PASS/FAIL

PASS

1/6 74HC05

AD5303/

AD5313/

AD5323

Figure 42. Window Detector Using AD5303/AD5313/AD5323

Coarse and Fine Adjustment Using the AD5303/AD5313/

AD5323

The DACs in the AD5303/AD5313/AD5323 can be paired

together to form a coarse and fine adjustment function, as

shown in Figure 43. DAC A is used to provide the coarse ad-

justment while DAC B provides the fine adjustment. Varying

the ratio of R1 and R2 will change the relative effect of the

coarse and fine adjustments. With the resistor values and exter-

nal reference shown, the output amplifier has unity gain for the

DAC A output, so the output range is 0 V to 2.5 V – 1 LSB.

For DAC B the amplifier has a gain of 7.6

× 10–3, giving DAC B

a range equal to 19 mV.

The circuit is shown with a 2.5 V reference, but reference volt-

ages up to VDD may be used. The op amps indicated will allow a

rail-to-rail output swing.

1 F

VREFA

VDD

GND

VOUTB

0.1 F

10 F

VDD = +5V

VOUT

VIN

GND

EXT

REF

AD820/

OP295

+5V

51.2k

390

AD780/REF192

WITH VDD = +5V

VOUTA

VREFB

390

51.2k

VOUT

AD5303/

AD5313/

AD5323

Figure 43. Coarse/Fine Adjustment

Daisy-Chain Mode

This mode is used for updating serially-connected or stand-

alone devices on the rising edge of SYNC. For systems that

contain several DACs, or where the user wishes to read back

the DAC contents for diagnostic purposes, the SDO pin may be

used to daisy-chain several devices together and provide serial

readback.

By connecting DCEN (Daisy-Chain Enable) pin high, the

Daisy-Chain Mode is enabled. It is tied low in the case of

Stand-Alone Mode. In Daisy-Chain Mode the internal gating

on SCLK is disabled. The SCLK is continuously applied to the

input shift register when SYNC is low. If more than 16 clock

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. This data is clocked out after the

falling edge of SCLK and is valid on the subsequent rising and

falling edges. By connecting this line to the DIN input on the

next DAC in the chain, a multiDAC interface is constructed.

Sixteen clock pulses are required for each DAC in the system.

Therefore, the total number of clock cycles must equal 16N

where N is the total number of devices in the chain. When the

serial transfer to all devices is complete, SYNC should be taken

high. This prevents any further data being clocked into the input

shift register.

A continuous SCLK source may be used if it can be arranged

that SYNC is held low for the correct number of clock cycles.

Alternatively, a burst clock containing the exact number of clock

cycles may be used and SYNC taken high some time later.

When the transfer to all input registers is complete, a common

LDAC signal updates all DAC registers and all analog outputs

are updated simultaneously.

68HC11*

MISO

SYNC

DIN

SCLK

MOSI

SCK

PC7

PC6

LDAC

SDO

SYNC

SCLK

LDAC

SDO

SYNC

SCLK

LDAC

SDO

DIN

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5303/

AD5313/

AD5323*

(DAC 1)

AD5303/

AD5313/

AD5323*

(DAC 2)

AD5303/

AD5313/

AD5323*

(DAC N)

Figure 44. Daisy-Chain Mode

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