AD73311ARS datasheet(15/36 Pages) AD

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AD73311

–15–

REV. B

SPORT Register Maps

There are two register banks for the AD73311: the control

bank consists of five read/write registers, each 8 bits wide. Table

IX shows the control register map for the AD73311. The first

two control registers, CRA and CRB, are reserved for control-

ling the SPORT. They hold settings for parameters such as bit

rate, internal master clock rate and device count (used when

more than one AD73311 is connected in cascade from a single

SPORT). The other three registers; CRC, CRD and CRE are

used to hold control settings for the ADC, DAC, Reference and

Power Control sections of the device. Control registers are

written to on the negative edge of SCLK. The data register

bank consists of two 16-bit registers that are the DAC and

ADC registers.

Master Clock Divider

The AD73311 features a programmable master clock divider

that allows the user to reduce an externally available master

clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro-

duce an internal master clock signal (DMCLK) that is used to

calculate the sampling and serial clock rates. The master clock

divider is programmable by setting CRB:4-6. Table VI shows

the division ratio corresponding to the various bit settings. The

default divider ratio is divide by one.

Table VI. DMCLK (Internal) Rate Divider Settings

MCD2

MCD1

MCD0

DMCLK Rate

MCLK

MCLK/2

MCLK/3

MCLK/4

MCLK/5

MCLK

Serial Clock Rate Divider

The AD73311 features a programmable serial clock divider that

allows users to match the serial clock (SCLK) rate of the data to

that of the DSP engine or host processor. The maximum SCLK

rate available is DMCLK and the other available rates are:

DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate

(DMCLK/8) is the default SCLK rate. The serial clock divider

is programmable by setting bits CRB:2–3. Table VII shows the

serial clock rate corresponding to the various bit settings.

Table VII. SCLK Rate Divider Settings

SCD1

SCD0

SCLK Rate

DMCLK/8

DMCLK/4

DMCLK/2

DMCLK

DAC Advance Register

The loading of the DAC is internally synchronized with the

unloading of the ADC data in each sampling interval. The de-

fault DAC load event happens one SCLK cycle before the

SDOFS flag is raised by the ADC data being ready. However,

this DAC load position can be advanced before this time by

modifying the contents of the DAC Advance field in Control

increments of weight 1/(DMCLK/8); see Table VIII. In certain

circumstances this can reduce the group delay when the ADC

and DAC are used to process data in series. Appendix E details

how the DAC advance feature can be used.

NOTE: The DAC advance register should be changed before

the DAC section is powered up.

Table VIII. DAC Timing Control

DA4

DA3

DA2

DA1

DA0

Time Advance*

0 ns

488.2 ns

976.5 ns

——

—

14.64

µs

15.13

µs

*DMCLK = 16.384 MHz.

SERIAL PORT

(SPORT)

SERIAL REGISTER

SCLK

DIVIDER

MCLK

DIVIDER

CONTROL

MCLK

(EXTERNAL)

RESETB

SDIFS

SDI

DMCLK

(INTERNAL)

SCLK

SDOFS

SDO

Figure 9. SPORT Block Diagram

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