AD73311ARS datasheet(17/36 Pages) AD

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AD73311

–17–

REV. B

Table XI. Control Register A Description

CONTROL REGISTER A

765

432

RESET

DC2

DC1

DC0

DLB

ALB

DATA/

PGM

Bit

Name

Description

DATA/

PGM

Operating Mode (0 = Program; 1 = Data Mode)

Mixed Mode (0 = Off; 1 = Enabled)

ALB

Analog Loop-Back Mode (0 = Off; 1 = Enabled)

DLB

Digital Loop-Back Mode (0 = Off; 1 = Enabled)

DC0

Device Count (Bit 0)

DC1

Device Count (Bit 1)

DC2

Device Count (Bit 2)

RESET

Software Reset (0 = Off; 1 = Initiates Reset)

Table XII. Control Register B Description

CONTROL REGISTER B

765

432

CEE

MCD2

MCD1

MCD0

SCD1

SCD0

Bit

Name

Description

Reserved

Must Be Programmed to 1

Reserved

Must Be Programmed to 1

SCD0

Serial Clock Divider (Bit 0)

SCD1

Serial Clock Divider (Bit 1)

MCD0

Master Clock Divider (Bit 0)

MCD1

Master Clock Divider (Bit 1)

MCD2

Master Clock Divider (Bit 2)

CEE

Control Echo Enable (0 = Off; 1 = Enabled)

Table XIII. Control Register C Description

CONTROL REGISTER C

765

4321

5VEN

PUREF

PUDAC PUADC

Bit

Name

Description

Power-Up Device (0 = Power Down; 1 = Power On)

Reserved

Must Be Programmed to 0

Reserved

Must Be Programmed to 0

PUADC

ADC Power (0 = Power Down; 1 = Power On)

PUDAC

DAC Power (0 = Power Down; 1 = Power On)

PUREF

REF Power (0 = Power Down; 1 = Power On)

REFOUT Use (0 = Disable REFOUT; 1 = Enable

REFOUT)

5VEN

Enable 5 V Operating Mode (0 = Disable 5 V Mode;

1 = Enable 5 V Mode)

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