AD7470 datasheet(4/16 Pages) AD

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REV. A

AD7470/AD7472

–4–

Limit at TMIN, TMAX

Parameter

AD7470

AD7472

Units

Description

fCLK

kHz min

MHz max

tCONVERT

436.42

531.66

ns min

tCLK = 1/fCLK IN

tWAKEUP

µs max

Wake-Up Time

ns min

CONVST Pulsewidth

ns max

CONVST to BUSY Delay, V

DD = 5 V

ns max

CONVST to BUSY Delay, V

DD = 3 V

ns max

BUSY to

CS Setup Time

ns max

CS to RD Setup Time

ns min

RD Pulsewidth

ns min

Data Access Time After Falling Edge of

ns max

Bus Relinquish Time After Rising Edge of

ns max

CS to RD Hold Time

135

ns min

Acquisition Time

t10

100

ns min

Quiet Time

NOTES

1Sample tested at +25

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of 1.6 V. See

Figure 1.

2Mark/Space ratio for the CLK input is 40/60 to 60/40. First CLK pulse should be 10 ns min from falling edge of

CONVST.

2 is 35 ns max @ +125

°C.

4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.

7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number i s then extrapolated

back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 7, quoted in the timing characteristics is the true bus relinquish

time of the part and is independent of the bus loading.

Specifications subject to change without notice.

TIMING SPECIFICATIONS1 (V

DD = +2.7 V to +5.25 V, REF IN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)

200 A

IOL

200 A

IOH

50pF

TO OUTPUT

+1.6V

Figure 1. Load Circuit for Digital Output Timing Specifications

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