PCA9539APW datasheet(8/39 Pages) NXP

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PCA9539A

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Product data sheet

Rev. 1 — 26 September 2012

8 of 39

NXP Semiconductors

PCA9539A

Low voltage 16-bit I2C-bus I/O port with interrupt and reset

6.3 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

either VDD or VSS. The external voltage applied to this I/O pin should not exceed the

recommended levels for proper operation.

6.4 Power-on reset

When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9539A

in a reset condition until VDD has reached VPOR. At that time, the reset condition is

released and the PCA9539A registers and I2C-bus/SMBus state machine initializes to

their default states. After that, VDD must be lowered to below VPORF and back up to the

operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset requirements”.

Table 12.

Configuration port 1 register (address 07h)

Bit

Symbol

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

At power-on reset, all registers return to default values.

Fig 6.

Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)

VDD

P0_0 to P0_7

P1_0 to P1_7

output port

configuration

data from

shift register

write

configuration

pulse

output port

write pulse

polarity

inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

002aah246

data from

shift register

VSS

to INT

ESD

protection

diode

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