AD7827 datasheet(3/12 Pages) AD

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–3–

REV. 0

AD7827

TIMING CHARACTERISTICS1, 2 (V

REFIN/REFOUT = 2.5 V, all specifications –40 C to +105 C, unless otherwise noted)

Parameter

5 V

10%

3 V

10%

Units

Conditions/Comments

tCONVERT

420

ns max

Conversion Time.

ns min

Minimum

CONVST Pulsewidth.

tCONVERT+t3

ns min

Falling edge of

CONVST to falling edge of RFS.

tCONVERT+t3+t7+t8

ns max

Rising edge of SCLK to falling edge of RFS.

ns max

Rising edge of SCLK to rising edge of RFS.

ns max

Rising edge of SCLK to high impedance disabled.

ns max

Rising edge of SCLK to DOUT valid delay.

ns min

Minimum high SCLK pulse duration.

ns min

Minimum low SCLK pulse duration.

ns min

Bus relinquish time after SCLK falling edge.

ns max

t10

ns max

Maximum delay from falling edge

CONVST to rising edge RFS if

RFS reset by

CONVST.

t11

ns min

Minimum time between end of serial read and next falling edge of

CONVST.

tPOWER-UP

µs max

Power-up time from rising edge of

CONVST using external 2.5 V

reference.

tPOWER-UP

µs max

Power-up time from rising edge of

CONVST using on-chip reference.

NOTES

1Sample tested to ensure compliance.

2See Figures 13, 14 and 15.

3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V

DD = 5 V ± 10% and time required for an

output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.

4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish time of

the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

50pF

OUTPUT

IOL

IOH

200 A

+2.1V

Figure 1. Load Circuit for Digital Output Timing Specifications

Parameter

Version B

Units

Test Conditions/Comments

POWER SUPPLY

VDD

4.5

V min

5 V

± 10% For Specified Performance

5.5

V max

2.7

V min

3 V

± 10% For Specified Performance

3.3

V max

IDD

Normal Operation

mA max

8 mA Typically

Power-Down

µA max

Logic Inputs = 0 V or VDD

Power Dissipation

VDD = 3 V

Normal Operation

mW max

Typically 24 mW

Power-Down

200 kSPS

9.58

mW max

1 MSPS

47.88

mW max

NOTES

1See Terminology section of this data sheet.

2Refer to the Analog Input section for an explanation of the Analog Input(s).

Specifications subject to change without notice.

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