AD7851 datasheet(18/36 Pages) AD

18 / 36 page

AD7851

–18–

REV. A

INPUT FREQUENCY – kHz

–72

–74

–90

0.91

100

13.4

25.7

38.3

50.3

–76

–78

–80

–88

–82

–84

–86

63.5

74.8

87.4

AVDD = DVDD = 5.0V

100mV pk-pk SINEWAVE ON AVDD

REFIN = 4.098 EXT REFERENCE

Figure 22. PSRR vs. Frequency

POWER-DOWN OPTIONS

The AD7851 provides flexible power management to allow the

user to achieve the best power performance for a given through-

put rate. The power management options are selected by pro-

gramming the power management bits, PMGT1 and PMGT0,

in the control register and by use of the SLEEP pin. Table VI

summarizes the power-down options that are available and how

they can be selected by using either software, hardware or a

combination of both. The AD7851 can be fully or partially pow-

ered down. When fully powered down, all the on-chip circuitry

is powered down and IDD is 1

µA typ. If a partial power-down is

selected, then all the on-chip circuitry except the reference is

powered down and IDD is 400 µA typ. The choice of full or par-

tial power-down does not give any significant improvement in

throughput with a power-down between conversions. This is dis-

cussed in the next section—Power-Up Times. But a partial

power-down does allow the on-chip reference to be used exter-

nally even though the rest of the AD7851 circuitry is powered

down. It also allows the AD7851 to be powered up faster after

a long power-down period when using the on-chip reference

(See Power-Up Times—Using On-Chip Reference).

When using the SLEEP pin, the power management bits

PMGT1 and PMGT0 should be set to zero (default status on

power-up). Bringing the SLEEP pin logic high ensures normal

operation, and the part does not power down at any stage. This

may be necessary if the part is being used at high throughput

rates when it is not possible to power down between conver-

sions. If the user wishes to power down between conversions at

lower throughput rates (i.e., <100 kSPS for the AD7851) to

achieve better power performances, then the SLEEP pin should

be tied logic low.

If the power-down options are to be selected in software only,

then the SLEEP pin should be tied logic high. By setting the

power management bits PMGT1 and PMGT0 as shown in

Table VI, a Full Power-Down, Full Power-Up, Full Power-

Down Between Conversions, and a Partial Power-Down

Between Conversions can be selected.

A combination of hardware and software selection can also be

used to achieve the desired effect.

Table VI. Power Management Options

PMGT1

PMGT0

SLEEP

Bit

Comment

Full Power-Down Between

Conversions (HW/SW)

Full Power-Up (HW/SW)

Full Power-Down Between

Conversions (SW)

Full Power-Down (SW)

Partial Power-Down Between

Conversions (SW)

NOTE

SW = Software selection, HW = Hardware selection.

0V TO VREF

INPUT

DIN AT DGND

=> NO WRITING

TO DEVICE

3-WIRE MODE

SELECTED

CURRENT, I = 12mA TYP

AVDD

DVDD

AIN(+)

AIN(–)

AMODE

CREF1

CREF2

SLEEP

DIN

DOUT

SYNC

SM1

SM2

CONVST

AGND

DGND

CLKIN

SCLK

REFIN/REFOUT

POLARITY

AD7851

ANALOG

(+5V)

SUPPLY

0.01µF

0.1µF

10µF

DVDD

UNIPOLAR RANGE

0.01µF

47nF

SERIAL MODE

SELECTION BITS

MASTER

CLOCK

INPUT

CONVERSION

START INPUT

SERIAL DATA OUTPUT

0.01µF

CAL

INTERNAL

REFERENCE

6/7MHz

OSCILLATOR

SERIAL CLOCK OUTPUT

285/ 333kHz PULSE

GENERATOR

OPTIONAL

EXTERNAL

REFERENCE

0.01µF

470nF

AUTO CAL ON

POWER-UP

REF198

AUTO POWER-

DOWN AFTER

CONVERSION

LOW POWER

µC/µP

Figure 23. Typical Low Power Circuit

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