–25–

REV. A

AD7851

MODE 2 (3-Wire SPI/QSPI Interface Mode)

This is the DEFAULT INTERFACE MODE.

In Figure 35 below we have the timing diagram for Interface

Mode 2 which is the SPI/QSPI interface mode. Here the SYNC

input is active low and may be pulsed or tied permanently low.

If SYNC is permanently low 16 clock pulses must be applied to

the SCLK pin for the part to operate correctly, and with a

pulsed SYNC input a continuous SCLK may be applied pro-

vided SYNC is low for only 16 SCLK cycles. In Figure 35 the

SYNC

going low disables the three-state on the DOUT pin.

The first falling edge of the SCLK after the SYNC going low

clocks out the first leading zero on the DOUT pin. The DOUT

SCLK rising edge as the part samples the input data on the

SCLK rising edge in this case. The POLARITY pin may be

used to change the SCLK edge which the data is sampled on

and clocked out on. If resetting the interface is required, the

SYNC

must be taken high and then low.

DB0

DB10

3-STATE

3-STATE

DB12

DB13

DB14

DB15

DB11

DB12

DB0

DB10

DB11

DB13

DB14

DB15

t

t

30/0.4 t

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

16

2345

16

SCLK (I/P)

t

9

t

5

t

11

t

3

t

10

t

12

DOUT (O/P)

t

8

DIN (I/P)

t

6

t

7

t

8

t

6

Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output and SYNC Input

(SM1 = SM2 = 0)

t

t

DB0

DB10

3-STATE

3-STATE

DB12

DB13

DB14

DB15

DB11

DB12

DB0

DB10

DB11

DB13

DB14

DB15

POLARITY PIN

LOGIC HIGH

SYNC (I/P)

16

2345

16

SCLK (I/P)

t

9

t

5

t

11

t

3

t

10

t

12

DOUT (O/P)

t

8

DIN (I/P)

t

6

t

7

t

8

t

6

Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)

MODE 3 (QSPI Interface Mode)

Figure 36 shows the timing diagram for Interface Mode 3. In

this mode the DSP is the master and the part is the slave. Here

the SYNC input is edge triggered from high to low, and the 16

clock pulses are counted from this edge. Since the clock pulses

are counted internally then the SYNC signal does not have to go

high after the 16th SCLK rising edge as shown by the dotted

SYNC

line in Figure 36. Thus a frame sync that gives a high

pulse, of one SCLK cycle minimum duration, at the beginning

of the read/write operation may be used. The rising edge of

SYNC

enables the 3-state on the DOUT pin. The falling edge

of SYNC disables the 3-state on the DOUT pin, and data is

clocked out on the falling edge of SCLK. Once SYNC goes

high, the 3-state on the DOUT pin is enabled. The data input is

sampled on the rising edge of SCLK and thus has to be valid a

used to change the SCLK edge which the data is sampled on

and clocked out on. If resetting the interface is required, the

SYNC

must be taken high and then low.