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MIPSZ2012D1R0 Datasheet(PDF) 31 Page - Panasonic Semiconductor |
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MIPSZ2012D1R0 Datasheet(HTML) 31 Page - Panasonic Semiconductor |
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31 / 48 page  31 AN30183A Ver. AEB GPEN — — GPDD — Default Name Bit 0 0 0 1 1 1 1 1 GPLD2 GPLD3 GPLD4 GROUP R/W 04h R/W Register Name Sub Address D5 D6 D7 Data D0 D1 D2 D3 D4 D7 : External pin ON/OFF control for LDO4 select register [0] : I2C control [1] : External pin control (default) D6 : External pin ON/OFF control for LDO3 select register [0] : I2C control [1] : External pin control (default) D5 : External pin ON/OFF control for LDO2 select register [0] : I2C control [1] : External pin control (default) D3 : External pin ON/OFF control for DCDC1 select register [0] : I2C control [1] : External pin control (default) D0 : External pin control permit register [0] : External pin control valid (default) [1] : External pin control invalid Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. OPERATION ( Continued ) * Please set it to normal mode when LDO starts. 3. Register map details |
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