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MIPSZ2012D1R0 Datasheet(PDF) 33 Page - Panasonic Semiconductor |
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MIPSZ2012D1R0 Datasheet(HTML) 33 Page - Panasonic Semiconductor |
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33 / 48 page ![]() 33 AN30183A Ver. AEB LD1PS LD2PS LD3PS LD4PS — Default Name Bit 0 0 0 0 0 0 — — — — — PSCNT R/W 05h R/W Register Name Sub Address D5 D6 D7 Data D0 D1 D2 D3 D4 D3 : LDO4 Power save mode select register [0] : Normal mode (default) [1] : Power save mode D2 : LDO3 Power save mode select register [0] : Normal mode (default) [1] : Power save mode D1 : LDO2 Power save mode select register [0] : Normal mode (default) [1] : Power save mode D0 : LDO1 Power save mode select register [0] : Normal mode (default) [1] : Power save mode *Please set it to normal mode when LDO starts. Note) The characteristics listed below are reference values derived from the design of the IC and are not guaranteed. OPERATION ( Continued ) 3. Register map details |
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