AD9660

REV. 0

–7–

tradeoff between output current droop when the control loops

are open, and the time it takes to calibrate and recalibrate the

laser power when the loops are closed.

The amount of output current droop is determined by the value

of the hold capacitor and the leakage current at that node.

When either of the two control loops are open (WRITE CAL or

BIAS CAL logic LOW), the pin connections for the hold

capacitors (WRITE HOLD and BIAS HOLD) are high imped-

ance inputs. Leakage currents will range from

±200 nA; this

low current minimizes the droop in the output power level. As-

suming the worst case current of

±200 nA, the output current

will change as follows:

±∆I

18

×10

−9

t

BIAS HOLD

C

BIAS HOLD

±∆I

18

×10

−9

t

WRITE HOLD

C

WRITE HOLD

To choose a value, the user will need to determine the amount

the maximum change in laser output power the application can

tolerate, and the laser efficiency (defined as the change in laser

output power to the change in laser diode current). As an ex-

ample, if an application requires 5 mW of laser power

±5%, and

the laser diode efficiency is 0.25 mW/mA, then

∆I

0. 25

mW

mA









= 1.0 mA

If the same application had a hold time requirement of 250

µs,

then the minimum value of the hold capacitor would be:

C

18

×10

1.0 mA

= 4.5 nF

When determining the calibration time, the T/H and the exter-

nal hold capacitor can be modeled using the simple RC circuit

illustrated in Figure 7.

R

AD9660

TZA

T/H

WRITE LEVEL

OR BIAS LEVEL

POWER MONITOR

WRITE HOLD

OR BIAS HOLD

EXTERNAL HOLD

CAPACITOR

Figure 7. Circuit Model for Determining Calibration Times

ode combinations that produce monitor currents that are less

ser output power than predicted, which may damage the laser

typical instead of minimum monitor current specifications. In

that case the input range to the AD9660 BIAS LEVEL and

WRITE LEVEL inputs should be limited to avoid damaging

laser diodes.

Although not recommended, another approach would be to

tion’s monitor current. The drawback to this approach is that

potentiometer’s stray inductance and capacitance may cause the

transimpedance amplifier to overshoot and degrade its settling,

potentiometer’s range.

larger than the recommended value will slow the response of the

amplifier. Lower values improve TZA bandwidth but may cause

the amplifier to oscillate.

Table I.

Recommended

≥2.5 kΩ

2 pF

1.5 k

Ω

3 pF

1 k

Ω

4 pF

500

Ω

8 pF

The circuit in Figure 6 allows an adjustable gain with low vari-

ance in bandwidth, but requires several external components.

50

Ω

GAIN

C1

POWER

MONITOR

R1

R2

R3

1.7k

Ω

2I PIN

1:2

SENSE

IN

AD9660

EQUIVALENT

CIRCUIT

50

Ω

(1+

+

)

R2

R1

R1

Figure 6. Adjustable Gain Configuration