REV. A

AD974

–10–

EXTERNAL DISCONTINUOUS CLOCK DATA READ

DURING CONVERSION WITH SYNC OUTPUT

GENERATED

Figure 7 illustrates the method by which data from conversion

“n-1” can be read during conversion “n” while using a discon-

tinuous external clock, with the generation of a SYNC output.

What permits the generation of a SYNC output is a transition of

DATACLK while either

CS is High or while both CS and R/C

are low. In Figure 7 a conversion is initiated by taking R/

C low

with

CS tied low. While this condition exists a transition of

DATACLK, clock pulse #0, will enable the generation of a

SYNC pulse. Less then 83 ns after R/

C is taken low the BUSY

output will go low to indicate that the conversion process has

begun. Figure 7 shows R/

C then going high and after a delay of

request the SYNC output. The SYNC output will appear ap-

proximately 40 ns after this rising edge and will be valid on the

falling edge of clock pulse #1 and the rising edge of clock pulse

#2. The MSB will be valid approximately 40 ns after the rising

edge of clock pulse #2 and can be latched off either the falling

edge of clock pulse #2 or the rising edge of clock pulse #3. The

LSB will be valid on the falling edge of clock pulse #17 and the

rising edge of clock pulse #18.

Data should be clocked out during the first half of

BUSY to

avoid degrading conversion performance. This requires use of a

10 MHz DATACLK or greater, with data being read out as

soon as the conversion process begins.

EXT

DATACLK

R/

C

BUSY

SYNC

DATA

0

BIT 15

(MSB)

BIT 14

BIT 0

(LSB)

1234

17

18

Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion

Using External Discontinuous Data Clock (EXT/

INT Set to Logic High, CS Set to Logic Low)