AD974 datasheet(18/20 Pages) AD

18 / 20 page

REV. A

AD974

–18–

–130

–90

–100

–110

–120

–70

–80

FREQUENCY – kHz

–60

–40

–50

–30

–10

–20

Figure 24. Adjacent Channel Crosstalk, Worst Pair (8192

Point FFT; AIN 2 = 220 kHz, –0.1 dB; AIN 1 = AGND)

MICROPROCESSOR INTERFACING

The AD974 is ideally suited for traditional dc measurement

applications supporting a microprocessor, and ac signal process-

ing applications interfacing to a digital signal processor. The

AD974 is designed to interface with a general purpose serial

port or I/O ports on a microcontroller. A variety of external

buffers can be used with the AD974 to prevent digital noise

from coupling into the ADC. The following sections illustrate

the use of the AD974 with an SPI equipped microcontroller and

the ADSP-2181 signal processor.

SPI INTERFACE

Figure 25 shows a general interface diagram between the

AD974 and an SPI equipped microcontroller. This interface

assumes that the convert pulses will originate from the micro-

controller and that the AD974 will act as the slave device. The

convert pulse could be initiated in response to an internal timer

interrupt. The reading of output data, one byte at a time,

if necessary, could be initiated in response to the end-of-

conversion signal (

BUSY going high).

+5V

SDI

SCK

I/O PORT

IRQ

SPI

DATA

DATACLK

BUSY

EXT/

INT

AD974

Figure 25. AD974-to-SPI Interface

ADSP-2181 INTERFACE

Figure 26 shows an interface between the AD974 and the

ADSP-2181 Digital Signal Processor. The AD974 is configured

for the Internal Clock mode (EXT/

INT = 0) and will therefore

act as the master device. The convert command is shown gener-

ated from an external oscillator in order to provide a low jitter

signal appropriate for both dc and ac measurements. Because

the SPORT, within the ADSP-2181, will be seeing a discontinu-

ous external clock, some steps are required to ensure that the

serial port is properly synchronized to this clock during each

data read operation. The recommended procedure to ensure

this is as follows:

• Enable SPORT0 through the System Control register.

• Set the SCLK Divide register to zero.

• Setup PF0 and PF1 as outputs by setting bits 0 and 1 in

PFTYPE.

• Force RFS0 low through PF0. The Receive Frame Sync

signal has been programmed active high.

• Enable AD974 by forcing

CS = 0 through PF1.

• Enable SPORT0 Receive Interrupt through the IMASK

• Wait for at least one full conversion cycle of the AD974 and

throw away the received data.

• Disable the AD974 by forcing

CS = 1 through PF1.

• Wait for a period of time equal to one conversion cycle.

• Force RFS0 high through PF0.

• Enable the AD974 by forcing

CS = 0 through PF1.

The ADSP-2181 SPORT0 will now remain synchronized to the

external discontinuous clock for all subsequent conversions.

DR0

SCLK0

PF1

RFS0

ADSP-2181

DATA

DATACLK

EXT/

INT

AD974

PF0

OSCILLATOR

SPORT0 CNTRL REG = 0 300F

Figure 26. AD974-to-ADSP-2181 Interface

POWER SUPPLIES AND DECOUPLING

The AD974 has two power supply input pins. VANA and VDIG

provide the supply voltages to the analog and digital portions,

respectively. VANA is the +5 V supply for the on-chip analog

circuitry, and VDIG is the +5 V supply for the on-chip digital

circuitry. The AD974 is designed to be independent of power

supply sequencing and thus free from supply voltage induced

latchup.

With high performance linear circuits, changes in the power

supplies can result in undesired circuit performance. Optimally,

well regulated power supplies should be chosen with less than

1% ripple. The ac output impedance of a power supply is a

complex function of frequency and will generally increase with

frequency. Thus, high frequency switching, such as that en-

countered with digital circuitry, requires the fast transient cur-

rents that most power supplies cannot adequately provide. Such

a situation results in large voltage spikes on the supplies. To

compensate for the finite ac output impedance of most supplies,

charge “reserves” should be stored in bypass capacitors. This

will effectively lower the supplies impedance presented to the

AD974 VANA and VDIG pins and reduce the magnitude of these

spikes. Decoupling capacitors, typically 0.1

µF, should be placed

close to the power supply pins of the AD974 to minimize any

inductance between the capacitors and the VANA and VDIG pins.

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