REV. 0

AD9806

–7–

TIMING SPECIFICATIONS

N

N+1

N+2

N+3

N+4

ADCCLK RISING EDGE PLACEMENT

N–0N–9N–8N–7N–6N–5

CCD

SHP

SHD

ADCCLK

D0–D9

NOTES:

1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.

2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (

3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.

4. OUTPUT LATENCY IS 9 CYCLES.

5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.

Figure 1. CCD-MODE Timing

N

N+1

N+2

N+3

N+4

N–9N–8N–7

N+5

VIDEO

INPUT

ADCCLK

D0–D9

N–6N–5

NOTE:

EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.

Figure 2. AUX-, AUXMID-, ADC-Mode Timing

CCD

SIGNAL

CLPOB

CLPDM

PBLK

EFFECTIVE

PIXELS

OPTICAL BLACK

BLANKING

INTERVAL

DUMMY BLACK

EFFECTIVE

PIXELS

NOTES:

1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.

2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.

3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.

4. CLPDM OVERWRITES PBLK.

5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.

Figure 3. CCD-MODE Clamp Timing