AD9806 datasheet(3/12 Pages) AD

3 / 12 page

REV. 0

–3–

AD9806

CCD-MODE SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

POWER CONSUMPTION

VDD = 2.7

VDD = 3.0

VDD = 3.3

MAXIMUM CLOCK RATE

MHz

CDS

Gain

0dB

Allowable CCD Reset Transient

500

Max Input Range before Saturation

1000

mV p-p

PGA

Gain Control Resolution

Bits

Gain Range (See Figure 5a for Gain Curve)

Low Gain (Code 95)

–1

Max Gain (1023)

BLACK LEVEL CLAMP

Clamp Level (Selected through Serial Interface E-Reg)

CLP0 (E-Reg 00)

LSB

CLP1 (E-Reg 01)

LSB

CLP2 (E-Reg 10)

LSB

CLP3 (E-Reg 11)

LSB

SIGNAL-TO-NOISE RATIO

3 (@ Low PGA Gain)

TIMING SPECIFICATIONS

Pipeline Delay

Cycles

Internal Clock Delay

5 (t

ID)3

Inhibited Clock Period (tINHIBIT)10

Output Delay (tOD)14.5

Output Hold Time (tHOLD)6

ADCCLK, SHP, SHD Clock Period

55.6

ADCCLK High-Level/Low-Level

SHP, SHD Minimum Pulsewidth

SHP Rising Edge to SHD Rising Edge

NOTES

1Input signal characteristics defined as follows:

1V MAX

INPUT

SIGNAL RANGE

200mV MAX

OPTICAL

BLACK PIXEL

500mV TYP

RESET

TRANSIENT

2Use equations on page 8 to calculate gain.

3SNR = 20 log

10 (Full-Scale Voltage/RMS Output Noise).

420 pF loading; timing shown in Figure 1.

5Internal aperture delay for actual sampling edge.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = fSHP = fSHD = 18 MHz, unless otherwise noted.)

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