ADG441/ADG442/ADG444

REV. 0

–5–

TRENCH ISOLATION

In the ADG441, ADG442 and ADG444, an insulating oxide

layer (trench) is placed between the NMOS and the PMOS

transistors of each CMOS switch. Parasitic junctions, which oc-

cur between the transistors in junction isolated switches, are

eliminated, the result being a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and

NMOS transistors form a diode that is reverse-biased under

normal operation. However, during overvoltage conditions, this

diode becomes forward biased. A silicon-controlled rectifier

(SCR) type circuit is formed by the two transistors causing a sig-

nificant amplification of the current which, in turn, leads to

latch up. With trench isolation, this diode is removed, the result

being a latch-up proof switch.

Trench isolation also leads to lower leakage currents. The

ADG441, ADG442 and ADG444 have a leakage current

of 0.5 nA as compared with a leakage current of several

nanoamperes in non-trench isolated switches. Leakage current is

an important parameter in sample-and-hold circuits, this current

being responsible for the discharge of the holding capacitor with

time causing droop. The ADG441/ADG442/ADG444’s low

leakage current, along with its fast switching speeds, make it

suitable for fast and accurate sample-and-hold circuits.

Typical Performance Characteristics

NMOS

PMOS

P-WELL

N-WELL

BURIED OXIDE LAYER

SUBSTRATE (BACK GATE)

TRENCH

LOCOS

Figure 1. Trench Isolation

170

10

15

90

50

3

0

130

9

612

150

110

70

30

100

20

15

60

40

–10

–15

80

10

0

–5

5