REV. 0

ADP3156

–6–

SD

DRIVE1

SENSE+

SENSE–

DRIVE2

PGND

AGND

CMP

12V

1k

1 F

4700pF

0.1 F

1.2V

100k

0.1 F

ADP3156

OP27

Figure 12. Closed-Loop Test Circuit for Accuracy

THEORY OF OPERATION

The ADP3156 uses a current-mode, constant-off-time control

technique to switch a pair of external N-channel MOSFETs in a

synchronous buck topology. Constant off-time operation offers

several performance advantages, including that no slope com-

pensation is required for stable operation. A unique feature of

the constant-off-time control technique is that since the off-time

is fixed, the converter’s switching frequency is a function of the

ratio of input voltage to output voltage. The fixed off-time is

programmed by the value of an external capacitor connected to

output voltage is maintained as described below in the cycle-by-

cycle operation. Under fixed operating conditions the on-time

does not vary, and it varies only slightly as a function of load.

This means that switching frequency is fairly constant in stan-

dard VRM applications. In order to maintain a ripple current in

the inductor, which is independent of the output voltage (which

also helps control losses and simplify the inductor design), the

off-time is made proportional to the value of the output voltage.

Normally, the output voltage is constant and therefore the off-

time is constant as well.

Active Voltage Positioning

The output voltage is sensed at the SENSE– pin. SENSE– is

connected to an internal voltage divider. The output of the

divider is then compared to the internal reference. A unique

supplemental regulation technique called active voltage posi-

tioning with optimal compensation adjusts the output voltage as

a function of the load current so that it is always optimally posi-

tioned for a load transient. Standard (passive) voltage position-

ing, sometimes recommended for use with other architectures,

has poor dynamic performance which renders it ineffective

under the stringent repetitive transient conditions specified in

Intel VRM documents. Consequently, such techniques do not

allow the minimum possible number of output capacitors to be

used. Optimally compensated active voltage positioning, as used

in the ADP3156, provides a bandwidth for transient response

that is limited only by parasitic output inductance. This yields

an optimal load transient response with the minimum number

of output capacitors.

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error amplifier and the current comparator (CMPI)

are the main control elements. (See the block diagram of Figure

3). During the on-time of the high side MOSFET, CMPI

monitors the voltage between the SENSE+ and SENSE– pins.

When the voltage level between the two pins reaches the thresh-

which turns off the high side MOSFET. The timing capacitor

troller. While the timing capacitor is discharging, the low side

drive output goes high, turning on the low side MOSFET. When

the voltage level on the timing capacitor has discharged to the

flip-flop. The output of the flip-flop forces the low side drive

output to go low and the high side drive output to go high. As a

result, the low side switch is turned off and the high side switch

is turned on. The sequence is then repeated. As the load current

increases, the output voltage starts to decrease. This causes an

increase in the output of the voltage-error amplifier, which, in

turn, leads to an increase in the current comparator threshold

tion of the external MOSFETs, feedback is incorporated to

sense the state of the driver output pins. Before the low side

drive output can go high, the high side drive output must be

low. Likewise, the high side drive output is unable to go high

while the low side drive output is high.

Power Good

The ADP3156 has an internal monitor that senses the output

voltage and drives the PWRGD pin of the device. This pin is an

open drain output whose high level (when connected to a pull-

up resistor) indicates that the output voltage has been within a

±5% regulation band of the targeted value for more than 500 µs.

The PWRGD pin will go low if the output is outside the regula-

tion band for more than 500

µs.

Output Crowbar

An added feature of using an N-channel MOSFET as the syn-

chronous switch is the ability to crowbar the output with the

same MOSFET. If the output voltage is 15% greater than the

targeted value, the ADP3156 will turn on the lower MOSFET,

which will current-limit the source power supply or blow its

fuse, pull down the output voltage, and thus save the micropro-

cessor from destruction. The crowbar function releases at ap-

proximately 50% of the nominal output voltage. For example, if

the output is programmed to 2.0 V, but is pulled up to 2.3 V or

above, the crowbar will turn on the lower MOSFET. If in this

case the output is pulled down to less than 1.0 V, the crowbar

will release, allowing the output voltage to recover to 2.0 V if

the fault condition has been removed.

Shutdown

The ADP3156 has a shutdown (SD) pin that is pulled down by

an internal resistor. In this condition the device functions nor-

mally. This pin should be pulled high to disable the output

drives.

APPLICATION INFORMATION

A number of power conversion requirements must be consid-

ered when designing an ACPI compliant system. In normal

operating mode, 12 V, 5 V and 3.3 V are available from the

main supply. These voltages need to be converted into the

appropriate supply voltages for the Northbridge core, the

Southbridge core and RAMBUS memory, as well as supplies for

GTL and I/O drivers, CMOS memory and clock and graphics

(AGP) circuits.