REV. 0

ADP3156

–7–

During the standby operating state, the 12 V, 5 V and 3.3 V

power supply outputs are disabled, and only a low power 5 V

rail (5VSB) is available. The circuits that must remain active in

standby must be able to run from 5VSB. To accomplish this,

power routing is required to allow switching between normal

and standby supplies. Lack of a 12 V rail in standby makes control

of linear outputs difficult, and with up to 8 A demand from the

1.5 V and 1.8 V rails, an all-linear solution is inefficient.

Figure 13 shows a typical ACP-compliant Pentium III / chipset

power management system using the ADP3155 and ADP3156.

The ADP3155 provides VID switched output and two linear

regulators for standby operation. A charge-pump-doubled 5VSB is

ORed into the supply rail to supply the linear regulators during

standby operation. The VID output collapses when the main

5 V rail collapses, but the N-channel MOSFET linear regu-

lators can continue to supply current from the ~9 V supply.

The ADP3156 provides 1.8 V via its main switching regulator,

and allows efficient linear regulation of 1.5 V rail by using the

1.8 V output as its source.

The design parameters for an ACPI-compliant Pentium III

peripheral system depend on what peripherals are used

(e.g., AGP) and what their specifications are. The following is

an example where the higher of two low system voltages (1.8 V

and 1.5 V) is created directly with the main buck converter, and

also used to supply power for the lower output voltage using the

ADP3156’s linear regulator controller.

5%

The absence of an inductor on the 1.5 V linear regulated output

allows the output current to respond quickly and the linear

regulator MOSFET’s resistance to be modulated quickly. This,

and some small bypassing capacitors, essentially insulates the

1.5 V output from transient activity on the 1.8 V output. How-

ever, this same fast response characteristic means that any 1.5 V

transient activity will be passed straight through the linear regu-

lator to the 1.8 V output. This means that the 1.8 V output filter

capacitor selection must consider both 1.8 V and 1.5 V load

transients.

In this design example, worst case consideration requires that

the 1.8 V output be designed for transient current loading of

tor design will have a current slew rate of <1 A/

µs due to the

inductor, nearly the entire 7 A transient current must be ab-

sorbed by the output capacitors.

high side N-channel MOSFET switch turns on, the voltage

2.3 V, a new on-time cycle is initiated. The value of the off-time

is calculated using the continuous-mode operating frequency.

an output voltage of 1.8 V, the corresponding off-time is:

t

V

Vf

s

OFF

O

IN

NOM

=













=

1

1

32

–.

µ

The timing capacitor can be calculated from the equation:

C

tA

V

pF

T

OFF

=

×

=

65

1

208

µ

5V_PM

POWER

MANAGEMENT

FUNCTIONS

12V

POWER MANAGEMENT

STATE COMMAND

5V_PM

ATX_POWER GOOD

PMSC

5V_PM

ATXPG

ADP3155

VID_4:0

LIN#2_

CTRLS

LIN#1_

CTRLS

MAIN_

CTRLS

SWITCHER

IN

CTRLS

OUT

LINEAR#1

IN

CTRLS

OUT

LINEAR#2

IN

CTRLS

OUT

5V

5V_PM

CPU

3.3V_PM

FOR POWER

MANAGEMENT

TRIPLE

OUTPUT

SUPPLY

VID

ADP3156

LIN_

CTRLS

MAIN_

CTRLS

12V

DUAL

OUTPUT

SUPPLY

IN

CTRLS

OUT

SWITCHER

5V

IN

CTRLS

OUT

LINEAR

3.3V_IN

1.5V_IN

VDDQ

POWER ROUTING

SELECT

3.3V

1.8V FOR

SB CORE,

MEM, ETC

1.5V VTT

FOR GTL

1.5V OR 3.3V

VDDQ FOR AGP

TYPEDET# FOR

AGP SELECT

ATX

(OR NLX)

POWER

SUPPLY

12V

5V

3.3V

5V_ALWAYS

ATX_PGOOD

ATX_SHUTDOWN

GND

12V

5V

3.3V

5V_PM

ATX_POWERGOOD

ATX_SHUTDOWN

2.5V_PM

FOR CMOS,

CLOCK, MEMORY

Figure 13. ACPI-Compliant Pentium III System Block Diagram