REV. 0

ADP3156

–9–

current of 1.7 A and an average short-circuit current of about

6.5 A—meaning that there is actually a small degree of short-

circuit current foldback. To safely carry the maximum current,

the sense resistor must have a power rating of at least (11.2 A –

1.07 A)

2

× 12.9 mW = 1.3 W.

Current Transformer Option

An alternative to using a low value and high power current sense

resistor is to reduce the sensed current by using a low cost cur-

rent transformer and a diode. The current can then be sensed

with a small size, low cost SMT resistor. Using a transformer

with one primary and 50 secondary turns reduces the worst-case

resistor dissipation to a few mW. Another advantage of using

this option is the separation of the current and voltage sensing,

which makes the voltage sensing more accurate.

Power MOSFETs

Two external N-channel power MOSFETs must be selected for

use with the ADP3156, one for the main switch, and an identi-

cal one for the synchronous switch. The main selection param-

dictates whether standard threshold or logic-level threshold

2.5 V) are strongly recommended. Only logic-level MOSFETs

should be used.

requirement for the two power MOSFETs. When the ADP3156

is operating in continuous mode, the simplifying assumption can

be made that one of the two MOSFETs is always conducting

maximum duty ratio of the high side FET is:

The duty ratio of the low side (synchronous rectifier) FET un-

der the maximum load condition is:

The maximum rms current of the high side FET is:

0.5

= 7.32

A rms

The maximum rms current of the low side FET is:

0.5

= 7.03

A rms

dissipation. Allowing 8% of the maximum output power for

FET dissipation, the total dissipation will be:

Allocating half of the total dissipation for the high side FET and

half for the low side FET, the required minimum FET resis-

tances will be:

Ω

Ω

Note that there is a trade-off between converter efficiency and

cost. Larger FETs reduce the conduction losses and allow

higher efficiency, but increase the system cost. If efficiency is

not a major concern, the International Rectifier IRL3103 is an

economical choice for both the high side and low side positions.

+25

°C. The low side FET is turned on with at least 10 V. The

high side FET, however, is turned on with only 12 V – 5 V =

7 V. Checking the typical output characteristics of the device in

the data sheet, shows that for an output current of 10 A, and at

tance increase due to the reduced gate drive can be neglected.

temperature of +140

°C must be modified by an R

plier, using the graph in the data sheet. In this case:

1.7

× 14 = 24 mΩ.

The high side FET dissipation is:

where the second term represents the turn-off loss of the FET.

provided by the ADP3156 is about 1 A.)

The low side FET dissipation is:

(Note that there are no switching losses in the low side FET.)

To maintain an acceptable MOSFET junction temperature,

proper heat sinking should be used. The heat sink and airflow

are chosen based on how low the impedance must be reduced in

order to keep the MOSFET’s junction temperature at an ac-

ceptably low level, according to the formula:

θ

where

θ

ent air (and depends on airflow),

mined maximum acceptable operating temperature of the

MOSFET, and the last two factors are the thermal resistance

from junction-to-case of the device, and case-to-heat sink. Typi-

cally, the junction-to-case thermal resistance is 2

°C/W, and the

case-to-heat sink resistance is 0.5

°C/W.

In continuous-inductor-current mode, the source current of the

To keep the input ripple voltage at a low value, one or more

capacitors with low equivalent series resistance (ESR) and ad-

equate ripple-current rating must be connected across the input

terminals. The maximum rms current of the input bypass ca-

pacitors is:

For an FA-type capacitor with 2700 mF capacitance and 10 V

voltage rating, the ESR is 34 m

Ω and the allowed ripple current

at 100 kHz (and similar frequencies) is 1.94 A. At +105

°C, two

such capacitors may be connected in parallel to handle the cal-

culated ripple current.

To further reduce the effect of the ripple voltage on the system

supply voltage bus and to reduce the input-current di/dt to

below the recommended maximum of 0.1 A/

µs, an additional

small inductor should be inserted between the converter and the

supply bus (see Figure 2).