ADV7172 datasheet(23/59 Pages) AD

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ADV7172/ADV7173

–23–

REV. A

OUTPUT VIDEO TIMING

The video timing generator generates the appropriate sync,

blank and burst sequence that controls the output analog wave-

forms. These sequences are summarized below. In slave modes,

the following sequences are synchronized with the input timing

control signals. In master modes, the timing generator free runs

and generates the following sequences in addition to the output

timing control signals.

NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always

blanked and vertical sync pulses are included. Scan Lines 525,

10–21 and 262, 263, 273-284 are also blanked and can be used

for closed captioning data. Burst is disabled on Lines 1–6, 261–

269 and 523–525.

NTSC–Noninterlaced: Scan Lines 1–9 are always blanked

and vertical sync pulses are included. Scan Lines 10–21 are also

blanked and can be used for closed captioning data. Burst is

disabled on Lines 1–6, 261–262.

PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are

always blanked and vertical sync pulses are included in Fields 1,

2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are always

blanked and vertical sync pulses are included in Fields 3, 4, 7

and 8. The remaining scan lines in the vertical blanking interval

are also blanked and can be used for teletext data. Burst is dis-

abled on Lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and

6. Burst is disabled on Lines 1–5, 311–319 and 623–625 in

Fields 3, 4, 7 and 8.

PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always

blanked and vertical sync pulses are included. The remaining

scan lines in the vertical blanking interval are also blanked and

can be used for teletext data. Burst is disabled on Lines 1–5,

310–312.

POWER-ON RESET

After power-up, it is necessary to execute a reset operation. A

reset occurs on the falling edge of a high-to-low transition on

the

RESET pin. This initializes the pixel port such that the pixel

inputs P7–P0 are not selected. After reset, the ADV7172/

ADV7173 is automatically set up to operate in NTSC/PAL

mode, depending on the PAL_NTSC pin. The subcarrier fre-

quency registers are automatically loaded with the correct values

for PAL or NTSC. All other registers, with the exception of

Mode Registers 1 and 2, are set to 00H. Mode Register 1 is set

to 07H. This is to ensure DACs D, E and F are ON after

power-up. All bits of Mode Register 2 are set to “0,” with the

exception of Bit 3 (i.e., Mode Register 2 reads 08H). Bit MR23

of Mode Register 2 is set to Logic “1.” This enables the 7.5 IRE

pedestal.

RESET SEQUENCE

When

RESET becomes active, the ADV7172/ADV7173 reverts

to the default output configuration. DACs A, B, C are off and

DACs D, E, F are powered on and output composite, luma and

chroma signals respectively. Mode Register 2, Bit 6 (MR26),

resets to “0.” The ADV7172/ADV7173 internal timing is under

the control of the logic level on the NTSC_PAL pin.

When

RESET is released Y, Cr, Cb values corresponding to a

black screen are input to the ADV7172/ADV7173. Output

timing signals are still suppressed at this stage.

When the user requires valid data, MR26 is set to “1” to allow

the valid pixel data to pass through the encoder. Digital output

timing signals become active and the encoder timing is now

under the control of the timing registers. If, at this stage, the

user wishes to select a video standard different from that on

the NTSC_PAL pin, Mode Register 2, Bit 5 (MR25) is set

(“1”) and the video standard required is selected by program-

ming Mode Register 0. Figure 36 illustrates the reset sequence

timing.

XXXXXXX

DIGITAL TIMING SIGNALS SUPPRESSED

BLACK VALUE

BLACK VALUE WITH SYNC

VALID VIDEO

TIMING ACTIVE

RESET

COMPOSITE/Y

CHROMA

MR26

PIXEL DATA VALID

DIGITAL TIMING

512

Figure 36.

RESET Sequence Timing Diagram

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