ADV7172 datasheet(27/59 Pages) AD

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ADV7172/ADV7173

–27–

REV. A

MODE REGISTER 0 MR0 (MR07–MR00)

(Address (SR4–SR0) = 00H)

Figure 44 shows the various operations under the control of

Mode Register 0.

MR0 BIT DESCRIPTION

Encode Mode Control (MR01–MR00)

These bits are used to set up the encoder mode. The ADV7172/

ADV7173 can be set up to output NTSC, PAL (B, D, G, H, I),

PAL M or PAL N standard video.

Luminance Filter Control (MR02–MR04)

These bits specify which luma filter is to be selected. The filter

selection is made independent of whether PAL or NTSC is

selected.

Chrominance Filter Control (MR05–MR07)

These bits select the chrominance filter. A low-pass filter can be

selected with a choice of cutoff frequencies, (0.65 MHz, 1.0 MHz,

1.3 MHz or 2 MHz) along with a choice of CIF or QCIF filters.

CHROMA FILTER SELECT

MR07 MR06

1.3 MHz LOW-PASS FILTER

0.65 MHz LOW-PASS FILTER

1.0 MHz LOW-PASS FILTER

2.0 MHz LOW-PASS FILTER

RESERVED

CIF

QCIF

RESERVED

MR05

MR01

MR00

MR07

MR02

MR03

MR05

MR06

MR04

OUTPUT VIDEO

STANDARD SELECTION

MR01 MR00

NTSC

PAL (B, D, G, H, I)

PAL (M)

PAL (N)

LUMA FILTER SELECT

MR04 MR03

LOW-PASS FILTER (NTSC)

LOW-PASS FILTER (PAL)

NOTCH FILTER (NTSC)

NOTCH FILTER (PAL)

EXTENDED MODE

CIF

QCIF

RESERVED

MR02

Figure 44. Mode Register 0 (MR0)

MR11

MR10

MR17

MR12

MR13

MR15

MR16

MR14

LOW POWER MODE

CONTROL

DISABLE

ENABLE

MR16

MR14

DAC A

DAC C CONTROL

MR15

MR17

(0)

ZERO SHOULD BE

WRITTEN TO

THIS BIT

POWER-DOWN

NORMAL

POWER-DOWN

NORMAL

DAC B

DAC C CONTROL

DAC C

DAC C CONTROL

MR13

POWER-DOWN

NORMAL

DAC E

DAC C CONTROL

MR11

POWER-DOWN

NORMAL

MR12

POWER-DOWN

NORMAL

DAC D

DAC C CONTROL

DAC F

DAC C CONTROL

MR10

POWER-DOWN

NORMAL

Figure 45. Mode Register 1 (MR1)

MODE REGISTER 1 MR1 (MR17–MR10)

(Address (SR4–SR0) = 01H)

Figure 45 shows the various operations under the control of

Mode Register 1.

MR1 BIT DESCRIPTION

DAC Control (MR15–MR10)

MR15–MR10 bits can be used to power down the DACs. This

can be used to reduce the power consumption of the ADV7172/

ADV7173 if any of the DACs are not required in the application.

Low Power Control (MR16)

This bit enables the lower power mode of the ADV7172/

ADV7173. This will reduce by approximately 50% the average

supply current consumed by each large DAC which is powered

on. For each DAC in low power mode, the relationship between

RSET1/VREF and the output current is unchanged by this (see

Appendix 8). This bit is only relevant to the larger DACs,

DACs A, B and C. DACs D, E and F are not affected by this low

power mode.

Reserved (MR17)

A Logic “0” must be written to this bit.

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