ADS4245 datasheet(39/66 Pages) TI

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ADS42B49

www.ti.com

SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013

CLKOUT DELAY PROG

Bits D[7:4]

CLKOUT DELAY PROG

These bits are useful to delay output clock in LVDS mode to optimize setup and hold time.

Typical delay in output clock obtained by these bits in LVDS mode is given below:

0000 = Default

0001 = 190 ps

0010 = 350 ps

0011 = 700 ps

0111 = 1000 ps

1011 = 1250 ps

1111 = 1450 ps

Others = Do not use

Bits D[3:0]

Always write '0'

EN DIGITAL

Bits D[7:1]

Always write '0'

Bit D0

EN DIGITAL: Digital function enable

0 = Default

1 = Digital functions including test pattern are enabled

LVDS CLKOUT

LVDS DATA

STBY

PDN GLOBAL

STRENGTH

Bit D7

STBY: Standby setting

0 = Normal operation

1 = Both channels are put in standby; wake-up time from this mode is fast (typically 50 µs).

Bit D6

LVDS CLKOUT STRENGTH: LVDS output clock buffer strength setting

0 = LVDS output clock buffer at default strength to be used with 100-

Ω external termination

1 = LVDS output clock buffer has double strength to be used with 50-

Ω external termination

Bit D5

LVDS DATA STRENGTH

0 = All LVDS data buffers at default strength to be used with 100-

Ω external termination

1 = All LVDS data buffers have double strength to be used with 50-

Ω external termination

Bits D[4:3]

Always write '0'

Bit D2

PDN GLOBAL

0 = Normal operation

1 = Total power down; all ADC channels, internal references, and output buffers are powered

down. Wake-up time from this mode is slow (typically 100 µs).

Bits D[1:0]

Always write '0'

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