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ADS4245 Datasheet(PDF) 21 Page - Texas Instruments |
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ADS4245 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 66 page  PowerSupply AVDD,DRVDD RESET SEN t 1 t 2 t 3 ADS42B49 www.ti.com SBAS558B – DECEMBER 2012 – REVISED JANUARY 2013 NOTE: A high pulse on the RESET pin is required in the serial interface mode when initialized through a hardware reset. For parallel interface operation, RESET must be permanently tied high. Figure 11. Reset Timing Diagram Table 9. Reset Timing (Only when Serial Interface is Used)(1) PARAMETER CONDITIONS MIN TYP MAX UNIT Delay from AVDD and DRVDD power-up to active RESET 1 ms t1 Power-on delay pulse 10 ns t2 Reset pulse width Active RESET signal pulse width 1 µs t3 Register write delay Delay from RESET disable to SEN active 100 ns (1) Typical values at +25°C; minimum and maximum values across the full temperature range: TMIN = –40°C to TMAX = +85°C, unless otherwise noted. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: ADS42B49 |
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