OUT

ESR

C

R

C8 =

R8

´

1

P

C6 =

2 f

R8

´

π

(

)

OUT

OVP

EA

OVPTH

R7

f

C

V

R8 =

1 D

Gm

V

´

´

´

-

´

π

(

)

2

OUT

ZRHP

OUT

V

1 D

f

=

2 L

I

´

-

´

π

OUT

P

OUT

OUT

2I

f

=

2 V

C

´

π

TPS61196

www.ti.com

SLVSBG1C – OCTOBER 2012 – REVISED FEBRUARY 2013

(12)

(13)

To make the loop stable, the loop must have sufficient phase margin at the crossover frequency where the loop

gain is 1. To avoid the effect of the right half plane zero on the loop stability, choose the crossover frequency

(14)

typical value is 120

(15)

capacitor which may have large ESR, a capacitor is required to cancel the zero of the output capacitor.

Equation 16 calculates the value of this capacitor.

(16)

Layout Consideration

As for all switching power supplies, especially those providing high current and using high switching frequencies,

layout is an important design step. If layout is not carefully done, the regulator could show instability as well as

EMI problems. Therefore, use wide and short traces for high current paths. The VDD capacitor, C3 (see in

SIMPLIFIED SCHEMATIC CIRCUIT) is the filter and noise decoupling capacitor for the internal linear regulator

powering the internal digital circuits. It should be placed as close as possible between the VDD and PGND pins

to prevent any noise insertion to digital circuits. The switch node at the drain of Q1 carries high current with fast

rising and falling edges. Therefore, the connection between this node to the inductor and the schottky diode

should be kept as short and wide as possible. It is also beneficial to have the ground of the capacitor C3 close to

the ground of the current sense resistor R7 since there is large driving current flowing between them. The ground

of output capacitor EC2 should be kept close to input power ground or through a large ground plane because of

the large ripple current returning to the input ground. When laying out signal grounds, it is recommended to use

short traces separate from power ground traces and connect them together at a single point, for example on the

thermal pad in the PWP package. Resistors R3, R4, R9, R10, R11 and R12 (see in the SIMPLIFIED

SCHEMATIC CIRCUIT) are setting resistors for switching frequency, LED current, protection threshold and

feedback voltage programming. To avoid unexpected noise coupling into the pins and affecting the accuracy,

these resistors need to be close to the pins with short and wide traces to GND. In PWP package, the thermal

pad needs to be soldered to the large ground plane on the PCB for better thermal performance. Additional

thermal via can significantly improve power dissipation of the IC.

Copyright © 2012–2013, Texas Instruments Incorporated

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