TPS61310 datasheet(32/57 Pages) TI

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Slave Address

R/W

Data

A/A

HS-MasterCode

F/SMode

HSMode

F/SMode

Data Transferred

(nxBytes + Acknowledge)

HSModeContinues

Slave Address

FromMasterto TPS6131x

From TPS6131xtoMaster

= Acknowledge

= START condition

= REPEATEDSTART condition

= STOP condition

Slave Address

R/W

Data

“0” Write

Slave Address

R/W

“1” Read

FromMasterto TPS6131x

From TPS6131xtoMaster

= Acknowledge

= START condition

= REPEATEDSTART condition

= STOP condition

Slave Address

R/W

Data

“0” Write

FromMasterto TPS6131x

From TPS6131xtoMaster

= Acknowledge

= START condition

= REPEATEDSTART condition

= STOP condition

TPS61310, TPS61311

SLVS978C – MARCH 2010 – REVISED NOVEMBER 2012

www.ti.com

TPS6131x I2C Update Sequence

The TPS6131x requires a start condition, a valid I2C address, a register address byte, and a data byte for a

single update. After the receipt of each byte, TPS6131x device acknowledges by pulling the SDA line low during

the high period of a single clock pulse. A valid I2C address selects the TPS6131x. TPS6131x performs an update

on the falling edge of the acknowledge signal that follows the LSB byte.

Figure 54. : “Write” Data Transfer Format in F/S-Mode

Figure 55. “Read” Data Transfer Format in F/S-Mode

Figure 56. Data Transfer Format in H/S-Mode

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TPS61310 Datasheet(PDF) 32 Page - Texas Instruments

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