12

Dust Networks

LTP5900 Mote Datasheet

Table 13

Mode 1 Pin Usage

Pin

I/O

Usage

RX

Input

Serial data moving from the microprocessor to the mote.

TX

Output

Serial data moving from the mote to the microprocessor.

MT_RTS

¯¯¯¯¯¯¯

Output

MT_RTS

¯¯¯¯¯¯¯ provides a mechanism to wake up the microprocessor in order to receive a

packet. This signal is asserted when the mote is ready to send a serial packet. The signal

stays low until the SP_CTS

¯¯¯¯¯¯¯ signal from the microprocessor is detected low by the mote

(indicating readiness to receive a packet) or the

¯¯¯¯¯¯¯ times out, it will de-

assert MT_RTS

¯¯¯¯¯¯¯ to attempt to send the

serial packet again (see Figure 9).

MT_RTS

¯¯¯¯¯¯¯ may be ignored by the microprocessor only if SP_CTS

¯¯¯¯¯¯¯ always stays low.

SP_CTS

¯¯¯¯¯¯¯

Input

SP_CTS

¯¯¯¯¯¯¯ provides packet-level flow control for packets transferred from the mote to the

microprocessor. When the microprocessor is capable of receiving a packet it should assert

the SP_CTS

¯¯¯¯¯¯¯ signal.

SP_CTS

¯¯¯¯¯¯¯ may be externally tied low (reducing pin count) only if the microprocessor is

always ready to receive a serial packet.

MT_CTS

¯¯¯¯¯¯¯

Output

MT_CTS

¯¯¯¯¯¯¯ provides packet-level flow control for packets transferred from the microprocessor

to the mote that are destined for transfer over the network. Upon reset, following boot the

mote will negate MT_CTS

¯¯¯¯¯¯¯ until the mote establishes a wireless network connection. During

operation, the mote will negate MT_CTS

¯¯¯¯¯¯¯ if the mote does not have sufficient buffering to

accept another packet. MT_CTS

¯¯¯¯¯¯¯ will also remain high if the mote is not part of the network.

The microprocessor must check that the MT_CTS

¯¯¯¯¯¯¯ pin is low before initiating each serial

packet for wireless transmission.

Note that the mote may receive local serial packets at any time regardless of the MT_CTS

¯¯¯¯¯¯¯

state. (For a list of local commands, see the SmartMesh IA-510 Mote Serial API Guide.)

TIME

¯¯¯¯

Input

The TIME

¯¯¯¯ pin can be used for triggering a timestamp packet. Its usage is optional.

8.3.2

Mode 3: Five-signal Serial Interface (115.2 kbps)

The LTP5900 mode 3 provides a five-signal serial interface with byte-level flow control on transfers from the mote to the

microprocessor. The mode 3 serial interface is comprised of the data pins (TX, RX) as well as handshake pins (MT_RTS

¯¯¯¯¯¯¯ ,

MT_CTS

¯¯¯¯¯¯¯ , SP_CTS

¯¯¯¯¯¯¯) used for bidirectional flow control. The MT_RTS

¯¯¯¯¯¯¯ signal is ideal for designs where the microprocessor

requires extra time to prepare to receive a packet (for example, the OEM microprocessor sleeps periodically, but requires a

wake-up signal prior to receiving a packet. Refer to Table 14 for information on each handshake pin, including details on

which pins are optional.

Table 14

Mode 3 Pin Usage

Pin

I/O

Usage

RX

Input

Serial data moving from the microprocessor to the mote.

TX

Output

Serial data moving from the mote to the microprocessor.

MT_RTS

¯¯¯¯¯¯¯

Output

MT_RTS

¯¯¯¯¯¯¯ provides a mechanism to wake up the microprocessor in order to receive a

packet. This signal is asserted when the mote is ready to send a serial packet. The signal

stays low until the SP_CTS

¯¯¯¯¯¯¯ signal from the microprocessor is detected low by the mote

(indicating readiness to receive a packet) or the tMT_RTS to SP_CTS timeout defined in

Section 8.3.3 expires. If MT_RTS

¯¯¯¯¯¯¯ times out, it will de-assert MT_RTS

¯¯¯¯¯¯¯, wait for tMT_RTS

retry and then re-assert MT_RTS

¯¯¯¯¯¯¯ to attempt to send the serial packet again (see

Figure 9).

SP_CTS

¯¯¯¯¯¯¯

Input

SP_CTS

¯¯¯¯¯¯¯ provides byte-level flow control for packets transferred from the mote to the

microprocessor. When the microprocessor is capable of receiving a packet it should assert

the SP_CTS

¯¯¯¯¯¯¯ signal. In mode 3 byte-level flow control is achieved by having the

microprocessor negate and then reassert the SP_CTS

¯¯¯¯¯¯¯ signal following the receipt of each

byte. The mote will begin transmission of the next byte after detecting the reassertion of