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LTC6417

6417f

applicaTions inForMaTion

The VOR pin, as shown in Figure 9, is internally connected

to a current source sourcing 2mA, plus an internal 20k

resistor pull-down to GND. An internal clamp limits the

maximum output to 3.4V. As soon as one of the inputs

goes beyond the limits, and therefore engages one of the

clamps, the output current, hence, the VOR voltage goes

to zero. The dynamic response of the VOR pin can be ad-

justed with an external resistor and an optional external

capacitor. For a high speed operation, add a 50Ω resistor

from VOR to GND, resulting in a high speed signal with

100mV swing.

The PWRADJ Pin

The voltage applied to the PWRADJ pin scales the supply

current and performance of the LTC6417. This is useful

for reducing power consumption in applications where

linearity of the LTC6417 exceeds the linearity of the other

components in the system; hence LTC6417’s linearity can

bederatedwithouteffectingsystemperformance.PWRADJ

is a high impedance input. It has an input impedance of

14.5k.Ona5Vsupply,PWRADJself-biasesto1.6V.Forfull

power, simply connect PWRADJ to the positive supply V+.

For minimum power, short the PWRADJ pin to GND. The

PWRADJ pin should be bypassed with a 0.1µF capacitor as

close to the LTC6417 as possible. LTC6417 performance

vs PWRADJ can be found in the graphs.

The SHDN Pin

When pulled high, the SHDN pin puts the LTC6417 in sleep

mode,significantlyreducingsupplycurrent.SHDNisahigh

impedance input. It has an input impedance of 10.5kΩ. If

theSHDNpinisnotdrivenwithanexternalvoltage,itfloats

down to the same potential as GND, keeping the LTC6417

enabled. The SHDN pin should be bypassed with a 0.1µF

capacitor as close to the LTC6417 as possible.

In sleep mode, the input and output stages are turned off,

but the input and output clamps are kept alive to protect

the part against overvoltage.

The supply current in sleep mode is only 24mA, instead

of the typical 125mA. But should the clamps turn on, the

current drawn from the supply can be as high as 180mA.

If a very large signal arrives at the LTC6417, the voltages

applied to the CLHI and VCM pins will determine the maxi-

mum and minimum output swing. Once the input signal

returnstothenormaloperatingrange,theLTC6417returns

to linear operation within 2ns. For DC-coupled operation,

the common mode of the input signals might be different

than the voltage on the VCM pin. The minimum swing will

stillbesetbythevoltagesappliedtotheVCMandCLHIpins.

CLHI is a high impedance input. It has an input impedance

of 4.8k. On a 5V supply, CLHI self-biases to 2.5V. To limit

the signal swing to a subsequent stage’s power supply,

e.g. an ADC such as the LTC2165, simply connect CLHI

to the positive supply pin of the LTC2165. The CLHI pin

should be bypassed with a 0.1µF capacitor as close to the

LTC6417 as possible.

The VOR Pin

The VOR, overrange pin signals an overrange condition

whenoneorbothinputsexceedtheminimumormaximum

signal swing limits set by the CLHI and VCM pins.

The LTC6417 VOR pin can be used by a control system to

limit the input power dynamically. This is very useful in

applications where the overload response of the complete

system would be too slow.

Figure 9. LTC6417 Internal Topology Showing

VOR Pin with Pull-Down Resistor and Clamp

6417 F09

VOR

20k

ICL

2mA

LTC6417

GND

V+

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