LT6201 datasheet(11/20 Pages) LINER

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LTC2314-14

231414f

For more information www.linear.com/2314-14

tTHROUGHPUT

tACQ-MIN

tACQ-MIN = 40ns

tCONV

tCONV(MIN) = 15 • tSCK + t2 + t10

SCK

SDO

HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B11

B12

B13*

231414 TD06

t10

Figure 6: LTC2314-14 Serial Interface Timing Diagram (SCK High During tACQ)

tTHROUGHPUT = 20 • tSCK

tACQ

tACQ = 4 • tSCK

tCONV

tCONV = 16 • tSCK

SCK

SDO

HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B11

B12

B13*

231414 TD07

t4 t7

t10

Figure 7: LTC2314-14 Serial Interface Timing Diagram (SCK Continuous)

applicaTions inForMaTion

tTHROUGHPUT

tACQ-MIN

tACQ-MIN = 40ns

tCONV

tCONV = 15.5 • tSCK + t2 + t10

SCK

SDO

HI-Z STATE

(MSB)

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

B11

B12

B13*

231414 F05

t10

Figure 5: LTC2314-14 Serial Interface Timing Diagram (SCK Low During tACQ)

Serial Data Output (SDO)

The SDO output is always forced into the high impedance

state while CS is high. The falling edge of CS starts the

conversion and enables SDO. The A/D conversion result

is shifted out on the SDO pin as a serial data stream with

the MSB first. The data stream consists of either one

leading zero (SCK held low during acquisition, Fig. 5) or

two leading zeros (SCK held high during acquisition, Fig.

6) followed by 14 bits of conversion data. There is 1 cycle

of conversion latency. Subsequent falling SCK edges after

the LSB is output will output zeros on the SDO pin. The

SDO output returns to the high impedance state after the

16th falling edge of SCK.

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