Aeroflex Circuit Technology

SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

10

Delay time, final data in of WRT operation to

DEAC or DCAB command

20

ns

Refresh interval

50

ms

Delay time, CS low or high to input enabled or

inhibited

0

0

cycle

Delay time, CKE high or low to CLK enabled or

disabled

1

1

cycle

Delay time, final data in of WRT operation to

READ, READ-P, WRT, or WRT-P

1

cycle

Delay time, ENBL or MASK command to

enabled or masked data in

0

0

cycle

Delay time, ENBL or MASK command to

enabled or masked data out

2

2

cycle

Delay time, DEAC or DCAB, command to DQ in

high-impedance state

CAS latency = 2

2

cycle

Delay time, WRT command to first data in

0

0

cycle

Delay time, STOP command to READ or WRT

command

2

cycle

† See Figure 2 - LVTTL Load Circuit for load circuits.

‡ All references are made to the rising transition of CLK, unless otherwise noted.

NOTES:

1.

referenced from the rising transition of CLK within the following cycle: CAS latency minus one cycle after the READ command. An access time is measured

at output reference level 1.5 V.

2. For read or write operations with automatic deactivate,

4. The temperature rise of

θ

AC Timing

†‡

(cont.)

(Vcc = 3.3V ±0.3V, Tc = -55°C to +110°C, See Note 4)

Parameter

Symbol

Test Conditions

Min

Max

Units