T8301 datasheet(2/190 Pages) AGERE

2 / 190 page

Table of Contents

Lucent Technologies Inc.

Advance Data Sheet

December 2000

Phone-On-A-Chip IP Solution DSP

T8301 Internet Protocol Telephone

Contents

Page

Tables

Page

1 Introduction .............................................................. 1

1.1 Features ............................................................ 1

2 Pin Information ........................................................ 3

2.1 T8301 100-Pin TQFP Pin Diagram ................... 3

2.2 Pinout Information ............................................. 4

3 Overview .................................................................. 7

4 DSP1600 Core ........................................................ 9

4.1 Bit Manipulation Unit (BMU) .............................. 9

4.2 Timer ................................................................. 9

4.3 Clock PLL Control ............................................. 9

4.4 Bit Input/Output (BIO) ...................................... 10

4.5 Serial Input/Output (SIO) ................................. 10

4.6 Interrupts and Traps ........................................ 10

4.7 Power Management ........................................ 11

4.8 External Memory Interface (EMI) .................... 11

4.9 T8301 Memory Mapping ................................. 11

4.10 Y Space Memory Map ................................... 15

5 Audio Input/Output Circuitry .................................. 17

5.1 Analog Audio Input Channels .......................... 17

5.2 Programmable Gain Amplifier (PGA) .............. 17

5.3 Analog Audio Output Channels ....................... 18

5.4 Tone Ringer ..................................................... 18

5.5 Audio Codec Block .......................................... 20

5.6 Audio Codec Control Registers ....................... 21

6 DMA Input/Output Channels .................................. 23

6.1 DMA Operation ................................................ 23

6.2 DMA Registers ................................................ 23

7 Hardware Compander ........................................... 26

8 Electrical Specifications ......................................... 28

8.1 Operating Range Specifications ...................... 28

8.2 Analog and Codec Specifications .................... 28

8.3 Crystal Specification ........................................ 29

9 JTAG and Hardware

Development System (HDS) ................................. 30

9.1 TMODE Control for JCS/Boundary-Scan

Operation ........................................................ 30

9.1.1 Mode 7 Operation (TMODE = 7) ............ 30

9.1.2 Mode 6 operation (TMODE = 6) ............ 30

9.2 The Principle of Boundary-Scan

Architecture ..................................................... 30

9.2.1 Boundary-Scan

Instruction Register ................................ 32

Figures

Page

Figure 1. T8301 TQFP Pin Diagram ........................... 3

Figure 2. DSP/ARM Interface Block Diagram ............. 7

Figure 3. T8301 Block Diagram .................................. 8

Figure 4. Crystal Oscillator ......................................... 9

Figure 5. Audio Codec Block Diagram ..................... 20

Figure 6. Hardware Compander Block Diagram ....... 27

Figure 7. Boundary-Scan Architecture ..................... 31

Table 1. Pin Description ............................................. 4

Table 2. SIO Interface Signals .................................. 10

Table 3. DSP1627 INT0N and INT1N ...................... 11

Table 4. T8301 Instruction/Coefficient

Memory Map .............................................. 13

Table 5. T8301 Memory-Mapped Peripherals .......... 14

Table 6. Data Memory Area: I/O,

Table 7. Programmable Gain Amplifier Maximum .... 17

Table 8. Tone Ringer Control Register (trc_reg) ...... 18

Table 9. Tone Ringer Amplitude

Control Encoding ........................................ 19

Table 10. Tone Ringer Frequency Encoding ............ 19

Table 11. aioc_reg Analog Audio I/O Control ...........21

Table 12. Audio Codec Clock

Control Register (aclkc_reg) ..................... 22

Table 13. Audio Clock Encoding .............................. 22

Table 14. DMA Control Register dmac_reg .............. 24

Table 15. DMA Starting Address

Table 16. DMA Transfer Count

Table 17. DMA Address Increment

Table 18. DMA Transfer Decrement Register

cntdec_reg ................................................ 25

Table 19. config_compander Register ...................... 26

Table 20. write_linear Register ................................. 26

Table 21. write_companded Register ....................... 26

Table 22. read_linear Register ................................. 26

Table 23. read_companded Register ....................... 26

Table 24. Operating Range Specifications ............... 28

Table 25. AINAN Specifications ...............................28

Table 26. AINCP, AINCN Specifications ..................28

Table 27. AOUTA Specifications .............................. 28

Table 28. Speaker#1, Speaker#2 Specifications ...... 29

Table 29. Digital Low-Pass Filters Specifications .....29

Table 30. Digital-to-Analog Converter

Specifications ........................................... 29

Table 31. Analog-to-Digital Converter

Specifications ........................................... 29

Table 32. Boundary-Scan Pin Functions ..................32

Table 33. Debug Mode .............................................. 32

Table 34. Boundary-Scan Instruction Register ......... 32

Table 35. Boundary-Scan Register Description ....... 33

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