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STM32F103RET6 Datasheet(PDF) 70 Page - STMicroelectronics |
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STM32F103RET6 Datasheet(HTML) 70 Page - STMicroelectronics |
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70 / 130 page ![]() Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 70/130 Doc ID 14611 Rev 8 Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) 1. CL = 15 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 27.7 ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 0.5 ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid 12 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 8 ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 ns |
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