Z86C30 datasheet(75/348 Pages) ZILOG

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Z8 CPU

User Manual

UM001602-0904

Watch–Dog Timer

WDT Time Select.

Bits D1 and D0 control a tap circuit that determines

the time-out period. Table 16 shows the different values that can be

obtained. The default value of D1 and D0 are 0 and 1, respectively.

WDT During HALT.

The D2 bit determines whether or not the WDT is

active during HALT mode. A 1 indicates active during HALT. The default

is 1. A WDT time out during HALT mode will reset control register ports

to their default reset conditions.

WDT During STOP.

The D3 bit determines whether or not the WDT is

active during STOP mode. Because XTAL clock is stopped during STOP

mode, unless as speciﬁed below, the on-board RC must be selected as the

clock source to the POR counter. A 1 indicates active during STOP. The

default is 1. If bits D3 and D4 are both set to 1, the WDT only, is driven

by the external clock during STOP mode. This feature makes it possible

to wake up from STOP mode from an internal source. Please refer to spe-

ciﬁc product speciﬁcations for conditions of control and port registers

when the Z8® CPU comes out of STOP mode. A WDT time out during

STOP mode will not reset all control registers. The reset conditions of the

ports from STOP mode due to WDT time out is the same as if recovered

using any of the other STOP mode sources.

Table 16. Time-Out Period of the WDT

Time-Out of

Typical Time-Out of

Internal RC OSC

System Clock

5 ms min

256 TpC

15 ms min

512 TpC

25 ms min

1024 TpC

100 ms min

4096 TpC

*Notes: The values given are for VCC = 5.0V. See the device product specification

for exact WDTMR time out select options available.

1. TpC = XTAL clock cycle

2. The default on reset is, D0 = 1 and D1 = 0.

Z86C30 Datasheet(PDF) 75 Page - Zilog, Inc.

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