Z86C30 datasheet(46/348 Pages) ZILOG

46 / 348 page

Z8 Family of Microcontrollers

User Manual

Address Space

UM001602-0904

gram memory the Z8® CPU offers multiplexed address/data lines (AD7–

AD0) on Port 1 and address lines (A15–A8) on Port 0. This feature only

applies to devices that offer Port 0 and Port 1. The maximum external

address is FFFF. This memory interface is supported by the control lines

AS (Address Strobe), DS (Data Strobe), and R/W (Read/Write). The ori-

gin of the external program memory starts after the last address of the

internal ROM. Figure 9 shows an example of external program memory

for the Z8® CPU.

External Data Memory

The Z8® CPU, in some cases, can address up to 60KB of external data

memory beginning at location 4096. External data memory (DM) can be

included with, or separated from, the external program memory space.

DM, an optional I/O function that can be programmed to appear on pin

P34, is used to distinguish between data and program memory space. The

state of the DM signal is controlled by the type of instruction being exe-

cuted. An LDC opcode references program memory (DM inactive) , and

an LDE instruction references data memory (DM active Low) . The user

must conﬁgure Port 3 Mode Register (P3M) bits D3 and D4 for this

mode.

Z86C30 Datasheet(PDF) 46 Page - Zilog, Inc.