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Z86C30 Datasheet(PDF) 28 Page - Zilog, Inc.

Part # Z86C30
Description  General-Purpose Register File. Flexible I/O. Analog Inputs
PDF  348 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C30 Datasheet(HTML) 28 Page - Zilog, Inc.

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Z8 Family of Microcontrollers
User Manual
Address Space
UM001602-0904
10
When instructions are executed, registers are read when defined as
sources and written when defined as destinations. All General-Purpose
Registers function as accumulators, address pointers, index registers,
stack areas, or scratch pad memory.
General-Purpose Registers
General-Purpose Registers (GPR) are undefined after the device is pow-
ered up. The registers keep their last value after any reset, as long as the
reset occurs in the VCC voltage-specified operating range. It will not keep
its last state from a VLV reset if VCC drops below 1.8v.
Registers in Bank E0-EF may only be accessed through the working regis-
ter and indirect addressing modes. Direct access cannot be used because
the 4-bit working register address mode already uses the format [E | dst],
where dst represents the working register number from 0h to Fh.
RAM Protect
The upper portion of the register file address space 80h to EFh (excluding
the control registers) may be protected from reading and writing. The
RAM Protect bit option is mask-programmable and is selected by the cus-
tomer when the ROM code is submitted. After the mask option is
selected, the user activates this feature from the internal ROM code to
turn off/on the RAM Protect by loading either a 0 or 1 into the IMR regis-
ter, bit D6. A 1 in D6 enables RAM Protect. Only devices that use regis-
ters 80h to EFh offer this feature.
Working Register Groups
Z8 instructions can access 8-bit registers and register pairs (16-bit words)
using either 4-bit or 8-bit address fields. 8-bit address fields refer to the
actual address of the register. For example, Register 58h is accessed by
calling upon its 8-bit binary equivalent, 01011000 (58h).
With 4-bit addressing, the register file is logically divided into 16 Work-
ing Register Groups of 16 registers each, as shown in Table 3. These 16
Note:



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