WM8788

Preliminary Technical Data

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PTD, December 2010, Rev 2.2

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ANALOGUE-TO-DIGITAL CONVERTER (ADC)

The WM8788 uses two 24-bit sigma-delta ADCs. The use of multi-bit feedback and high

oversampling rates reduces the effects of jitter and high frequency noise. All common sample rates

from 8kHz to 192kHz are supported; these are selected as described in the “Digital Audio Interface”

section.

Digital filters are also incorporated on the ADC output signal path to remove DC offsets and other

unwanted noise. The cut-off frequency of the ADC high-pass filter varies with the ADC sample rate

(fs), but is typically 4Hz when fs = 48kHz.

Filter response plots for the ADC high-pass filter are shown in “Digital Filter Characteristics”.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for outputting ADC data from the WM8788. It uses three pins:

•

ADCDAT - ADC data output

•

LRCLK - Left / Right data alignment clock

•

BCLK - Bit clock, for synchronisation

The configuration of the digital audio interface is determined by the logic levels on the following

hardware control pins:

•

MASTER - Master / Slave mode select

•

OSR - ADC Oversample rate select

•

AIFMODE0 - Audio Interface configuration select 0

•

AIFMODE1 - Audio Interface configuration select 1

The digital audio interface supports Right-justified, Left-justified and I2S formats. The data word size

can be 16, 20 or 24-bits.

Audio sample rates (fs) from 8kHz to 192kHz are supported. A master clock (MCLK) is required at

one of the typical clocking ratios 128fs, 192fs, 256fs, 384fs, 512fs and 768fs.

The WM8788 can operate in master mode or in slave mode. In master mode, LRCLK and BCLK are

generated by the WM8788. In slave mode, LRCLK and BCLK are inputs to the WM8788.

The digital audio interface is configured using the hardware control pins MASTER, OSR, AIFMODE0

and AIFMODE1. Note that these pins are tri-state digital inputs. The logic 1 and logic 0 voltage levels

are referenced to the AVDD power domain. A logic ‘Z’ is a high-impedance condition which is

selected when the pin is floating and not connected.

A description of the hardware control pins is provided in the “Digital Audio Interface Control” section

below.

The digital audio interface protocols are described in the “Master and Slave Mode Operation” and

“Audio Data Formats” sections.