WM8788

Preliminary Technical Data

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PTD, December 2010, Rev 2.2

14

For Master Mode, set MASTER and OSR according to the applicable sample rate and clocking ratio.

MASTER

OSR

CLOCKING RATIO

SAMPLE RATE

1

0

384fs

8, 16, 32, 44.1, 48kHz

1

1

384fs

88.2, 96kHz

Z

0

256fs

8, 16, 32, 44.1, 48kHz

Z

1

256fs

88.2, 96kHz

Table 4 Master Mode Configuration

In Master Mode, the sample rate (fs) is determined by the MCLK frequency and by the selected

clocking ratio. The LRCLK frequency is the same as the sample rate, and is output by the WM8788

in master mode.

The BCLK signal is output by the WM8788 in master mode. The BCLK frequency is LRCLK x 64.

MASTER AND SLAVE MODE OPERATION

The digital audio interface can be configured as a Master or a Slave interface, depending on the

state of the MASTER control pin described earlier. The two modes are illustrated in Figure 6 and

Figure 7.

Figure 6 Master Mode

Figure 7 Slave Mode

In Master mode, LRCLK and BCLK are configured as outputs, and the WM8788 controls the timing

of the data transfer on the ADCDAT pin.

In Master mode, the LRCLK frequency is determined automatically according to the MCLK frequency

and the selected clocking ratio. The BCLK frequency is LRCLK x 64.

In Slave mode, LRCLK and BCLK are configured as inputs, and the data timing is controlled by an

external master.

AUDIO DATA FORMATS

Three audio data formats are supported by the digital audio interface:

•

Right-justified

•

Left-justified

•

All of these modes are MSB first, and are illustrated below. Refer to the “Signal Timing

Requirements” section for timing information.

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition.