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STM32F407IG Datasheet(PDF) 99 Page - STMicroelectronics

Part # STM32F407IG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  167 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IG Datasheet(HTML) 99 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 2
99/167
5.3.16
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 44 are derived from tests
performed under the conditions summarized in Table 11. All I/Os are CMOS and TTL
compliant.
Table 44.
I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
TTL ports
2.7 V
≤ VDD ≤ 3.6 V
VSS–0.3
-
0.8
V
VIH
(1)
TTa/TC(2) I/O input high level voltage
2.0
-
VDD+0.3
FT(3) I/O input high level voltage
2.0
-
5.5
VIL
Input low level voltage
CMOS ports
1.8 V
≤ VDD ≤ 3.6 V
VSS–0.3
-
0.3VDD
VIH
(1)
TTa/TC I/O input high level voltage
0.7VDD
-3.6(4)
FT I/O input high level voltage
-5.2(4)
CMOS ports
2.0 V
≤ VDD ≤ 3.6 V
-5.5(4)
Vhys
I/O Schmitt trigger voltage hysteresis(5)
-200
-
mV
IO FT Schmitt trigger voltage
hysteresis(5)
5% VDD
(4)
-
-
Ilkg
I/O input leakage current (6)
VSS ≤ VIN ≤ VDD
--
±1
µA
I/O FT input leakage current (6)
VIN = 5V
-
-
3
RPU
Weak pull-up equivalent
resistor(7)
All pins
except for
PA10 and
PB12
VIN = VSS
30
40
50
k
Ω
PA10 and
PB12
811
15
RPD
Weak pull-down
equivalent resistor
All pins
except for
PA10 and
PB12
VIN = VDD
30
40
50
PA10 and
PB12
811
15
CIO
(8)
I/O pin capacitance
5
pF
1.
If VIH maximum value cannot be respected, the injection current must be limited externally to IINJ(PIN) maximum value.
2.
TTa = 3.3 V tolerant I/O directly connected to ADC; TC = standard 3.3 V I/O.
3.
FT = 5 V tolerant.
4.
With a minimum of 100 mV.
5.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
6.
Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.
7.
Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order)
.
8.
Guaranteed by design, not tested in production.



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