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STM32F407IG Datasheet(PDF) 114 Page - STMicroelectronics

Part # STM32F407IG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  167 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IG Datasheet(HTML) 114 Page - STMicroelectronics

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Electrical characteristics
STM32F405xx, STM32F407xx
114/167
Doc ID 022152 Rev 2
Figure 42.
USB OTG FS timings: definition of data signal rise and fall time
Table 56.
USB OTG FS electrical characteristics(1)
1.
Guaranteed by design, not tested in production.
Driver characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
2.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
CL = 50 pF
420
ns
tf
Fall time(2)
CL = 50 pF
4
20
ns
trfm
Rise/ fall time matching
tr/tf
90
110
%
VCRS
Output signal crossover voltage
1.3
2.0
V
Table 57.
USB FS clock timing parameters(1)(2)
1.
Guaranteed by design, not tested in production.
2.
TBD stands for “to be defined”.
Parameter
Symbol
Min
Nominal
Max
Unit
fHCLK value to guarantee proper operation of
USB FS interface
-
14.2
MHz
Frequency (first transition)
8-bit ±10%
FSTART_8BIT
TBD
TBD
TBD
MHz
Frequency (steady state) ±500 ppm
FSTEADY
TBD
TBD
TBD
MHz
Duty cycle (first transition)
8-bit ±10%
DSTART_8BIT
TBD
TBD
TBD
%
Duty cycle (steady state) ±500 ppm
DSTEADY
TBD
TBD
TBD
%
Time to reach the steady state frequency and
duty cycle after the first transition
TSTEADY
--
TBD
ms
Clock startup time after the
de-assertion of SuspendM
Peripheral
TSTART_DEV
--
TBD
ms
Host
TSTART_HOST
--
-
PHY preparation time after the first transition
of the input clock
TPREP
--
-
µs
ai14137
tf
Differen tial
data lines
VSS
VCRS
tr
Crossover
points



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