ACE25C512

512K-BIT Serial Flash Memory

VER 1.2

4

Pin descriptions

Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and

output operations.

and Dual SPI operation. Standard SPI instructions use the unidirectional DI (input) pin to serially write

instructions, addresses or data to the device on the rising edge of the Serial Clock (CLK) input pin.

Standard SPI also uses the unidirectional DO (output) to read data or status from the device on the

falling edge of CLK.

Dual SPI instructions use the bidirectional DQ pins to serially write instructions, addresses or data to

the device on the rising edge of CLK and read data or status from the device on the falling edge of

CLK.

Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation. When

impedance. When deselected, the devices power consumption will be at standby levels unless an

internal erase, program or write status register cycle is in progress. When CS# is brought low, the

device will be selected, power consumption will increase to active levels and instruct ions can be

written to and data read from the device. After power -up, CS# must transition from high to low before

a new instruction will be accepted. The CS# input must track the VCC supply level at power -up (see

“9 Write Protection” and Figure 23). If needed a pull-up resister on CS# can be used to accomplish

this.

HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected. When

HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI

and CLK pins will be ignored (don’t care). When HOLD# is brought high, device operation can resume.

The HOLD# function can be useful when multiple devices are sharing the same SPI signals. The

HOLD# pin is active low.

Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers from

being written. Used in conjunction with the Status Register’s Block Protect (BP2, BP1 and BP0) bits

and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire me mory array

can be hardware protected. The WP# pin is active low.

Memory Organization

The ACE25C512 array is organized into 256 programmable pages of 256-bytes each. Up to 256

bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in

groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase)

or the entire chip (chip erase). The ACE25C512 has 16 erasable sectors 2 erasable 32-k byte blocks

and 1 erasable 64-k byte block respectively. The small 4KB sectors allow for greater flexibility in

applications that require data and parameter storage.

Block (64KB)

Sector (4KB)

Address Range

0

15

00F000h

00FFFFh

.

.

.

.

.

.

3

003000h

003FFFh

2

002000h

002FFFh