ACE25C512

512K-BIT Serial Flash Memory

VER 1.2

11

Figure 5 Write enable instruction

Write disable (WRDI) (04h)

The Write Disable (WRDI) instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status

Register to a 0. The Write Disable (WRDI) instruction is entered by driving CS# low, shifting the

instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL bit is automatically

reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,

Block Erase, Chip Erase instructions.

Figure 6 Write disable instruction

Read status register (RDSR) (05h)

The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is

entered by driving CS# low and shifting the instruction code “05h” into the DI pin on the rising edge of

CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first as shown in Figure 7. The Status Register bits are shown in Figure 4 and

include the WIP, WEL, BP2-BP0 and SRP bits.

The Read Status Register instruction may be used at any time, even while a Program, Erase or Write

Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when

the cycle is complete and if the device can accept another instruction. The Status Register can be

read continuously. The instruction is completed by driving CS# high.