MPC974

MOTOROLA

TIMING SOLUTIONS

BR1333 — Rev 6

4

PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)

Symbol

Characteristic

Min

Max

Unit

Condition

tr, tf

TCLK Input Rise/Falls

3.0

ns

fref

Reference Input Frequency

Note 3.

Note 3.

MHz

frefDC

Reference Input Duty Cycle

25

75

%

3. Input reference frequency is limited by the divider selection and the VCO lock range.

AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

tr, tf

Output Rise/Fall Time (Note 4.)

0.15

1.5

ns

0.8 to 2.0V

tpw

Output Duty Cycle (Note 4.)

tCYCLE/2

–800

tCYCLE/2

±500

tCYCLE/2

+800

ps

fVCO

PLL VCO Lock Range

fseln, fselFBn =

÷4 to ÷12

200

500

MHz

Note 5.

tpd

SYNC to Feedback Propagation Delay

–250

100

ps

Notes 4., 6.

tos

Output-to-Output Skew

350

ps

Note 4.

fmax

Maximum Output Frequency

Q (

÷2)

Q (

÷4)

Q (

÷6)

125

63

42

MHz

VCO_Sel = 0

tPZL

Output Enable Time

2

10

ns

tPLZ, tPHZ

Output Disable Time

2

10

ns

tjitter

Cycle–to–Cycle Jitter (Peak–to–Peak)

±100

ps

tlock

Maximum PLL Lock Time

10

ms

4. 50

Ω transmission lines terminated to VCC/2.

5. The PLL will be unstable if the total divide between the VCO and the feedback pin is less < 8. VCO_SEL = ‘0’, fsela or fselb = ‘0’ cannot be used

for the PLL feedback signal.

6. tpd is specified for 50MHz input reference. The window will shrink/grow proportionally from the minimum limit with shorter/longer input reference

periods. The tpd does not include jitter.

APPLICATIONS INFORMATION

Programming the MPC974

The MPC974 clock driver outputs can be configured into

several frequency relationships, in addition the external

feedback option allows for a great deal of flexibility in

establishing unique input–to–output frequency relationships.

The output dividers for the four output groups allows the user

to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 frequency

ratios. The use of even dividers ensures that the output duty

cycle is always 50%. Function Table 1 illustrates the various

output configurations, the table describes the outputs using

the VCO frequency as a reference. As an example for a 3:2:1

relationship the Qa outputs would be set at VCO/2, the Qb’s

and Qc’s at VCO/4 and the Qd’s at VCO/6. These settings

will provide output frequencies with a 3:2:1 relationship.

The division settings establish the output relationship, but

one must still ensure that the VCO will be stable given the

frequency of the outputs desired. The VCO lock range can be

found in the specification tables. The feedback frequency

should be used to situate the VCO into a frequency range in

which the PLL will be stable. The design of the PLL is such

that for output frequencies between 10 and 125MHz the

MPC974 can generally be configured into a stable region.

The relationship between the input reference and the

output frequency is also very flexible. The separate PLL

feedback output allows for a wide range of output vs input

frequency relationships. Function Table 1 can be used to

identify the potential relationships available. Figure 3

illustrates several programming possibilities, although not

exhaustive it is representative of the potential applications.

Using the MPC974 as a Zero Delay Buffer

The external feedback option of the MPC974 clock driver

allows for its use as a zero delay buffer. By using one of the

outputs as a feedback to the PLL the propagation delay

through the device is near zero. The PLL works to align the

output edge with the input reference edge thus producing a

near zero delay. The static phase offset is a function of the

input reference frequency of the MPC974. The Tpd of the

device is specified in the specification tables.